Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4238834 [patent_doc_number] => 06088759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/885117 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14912 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088759.pdf [firstpage_image] =>[orig_patent_app_number] => 885117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885117
Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture Jun 29, 1997 Issued
Array ( [id] => 4057380 [patent_doc_number] => 05996048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Inclusion vector architecture for a level two cache' [patent_app_type] => 1 [patent_app_number] => 8/879530 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3237 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996048.pdf [firstpage_image] =>[orig_patent_app_number] => 879530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879530
Inclusion vector architecture for a level two cache Jun 19, 1997 Issued
Array ( [id] => 1601967 [patent_doc_number] => 06385688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Asynchronous interface for a nonvolatile memory' [patent_app_type] => B1 [patent_app_number] => 08/877840 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385688.pdf [firstpage_image] =>[orig_patent_app_number] => 08877840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877840
Asynchronous interface for a nonvolatile memory Jun 17, 1997 Issued
Array ( [id] => 4202359 [patent_doc_number] => 06094704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Memory device with pipelined address path' [patent_app_type] => 1 [patent_app_number] => 8/877133 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094704.pdf [firstpage_image] =>[orig_patent_app_number] => 877133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877133
Memory device with pipelined address path Jun 16, 1997 Issued
Array ( [id] => 1481042 [patent_doc_number] => 06389509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Memory cache device' [patent_app_type] => B1 [patent_app_number] => 08/866426 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 18069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389509.pdf [firstpage_image] =>[orig_patent_app_number] => 08866426 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866426
Memory cache device May 29, 1997 Issued
Array ( [id] => 4018549 [patent_doc_number] => 05924124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Software programmable bus disable system' [patent_app_type] => 1 [patent_app_number] => 8/863266 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2742 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924124.pdf [firstpage_image] =>[orig_patent_app_number] => 863266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863266
Software programmable bus disable system May 26, 1997 Issued
Array ( [id] => 4290300 [patent_doc_number] => 06308247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Page table entry management method and apparatus for a microkernel data processing system' [patent_app_type] => 1 [patent_app_number] => 8/861684 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12112 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308247.pdf [firstpage_image] =>[orig_patent_app_number] => 861684 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861684
Page table entry management method and apparatus for a microkernel data processing system May 21, 1997 Issued
Array ( [id] => 4061117 [patent_doc_number] => 05895500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Data processing system with reduced look-up table for a function with non-uniform resolution' [patent_app_type] => 1 [patent_app_number] => 8/858332 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7097 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895500.pdf [firstpage_image] =>[orig_patent_app_number] => 858332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858332
Data processing system with reduced look-up table for a function with non-uniform resolution May 18, 1997 Issued
Array ( [id] => 4033822 [patent_doc_number] => 05963984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Address translation unit employing programmable page size' [patent_app_type] => 1 [patent_app_number] => 8/857300 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7925 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963984.pdf [firstpage_image] =>[orig_patent_app_number] => 857300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857300
Address translation unit employing programmable page size May 15, 1997 Issued
Array ( [id] => 3798213 [patent_doc_number] => 05809532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Data processor with cache and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/850368 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5976 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809532.pdf [firstpage_image] =>[orig_patent_app_number] => 850368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850368
Data processor with cache and method of operation May 1, 1997 Issued
Array ( [id] => 4020445 [patent_doc_number] => 05860157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Nonvolatile memory card controller with an optimized memory address mapping window scheme' [patent_app_type] => 1 [patent_app_number] => 8/850653 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6351 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860157.pdf [firstpage_image] =>[orig_patent_app_number] => 850653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850653
Nonvolatile memory card controller with an optimized memory address mapping window scheme May 1, 1997 Issued
Array ( [id] => 4011733 [patent_doc_number] => 05893166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Addressing method and system for sharing a large memory address space using a system space global memory section' [patent_app_type] => 1 [patent_app_number] => 8/847046 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6678 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893166.pdf [firstpage_image] =>[orig_patent_app_number] => 847046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847046
Addressing method and system for sharing a large memory address space using a system space global memory section Apr 30, 1997 Issued
Array ( [id] => 4160580 [patent_doc_number] => 06061771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Cross-system data piping system using an external shared memory' [patent_app_type] => 1 [patent_app_number] => 8/846714 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7578 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061771.pdf [firstpage_image] =>[orig_patent_app_number] => 846714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846714
Cross-system data piping system using an external shared memory Apr 29, 1997 Issued
Array ( [id] => 4259962 [patent_doc_number] => 06092166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Cross-system data piping method using an external shared memory' [patent_app_type] => 1 [patent_app_number] => 8/846718 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7574 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092166.pdf [firstpage_image] =>[orig_patent_app_number] => 846718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846718
Cross-system data piping method using an external shared memory Apr 29, 1997 Issued
Array ( [id] => 4059678 [patent_doc_number] => 05875470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Multi-port multiple-simultaneous-access DRAM chip' [patent_app_type] => 1 [patent_app_number] => 8/841029 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7383 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875470.pdf [firstpage_image] =>[orig_patent_app_number] => 841029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841029
Multi-port multiple-simultaneous-access DRAM chip Apr 28, 1997 Issued
Array ( [id] => 3991248 [patent_doc_number] => 05905993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Flash memory card with block memory address arrangement' [patent_app_type] => 1 [patent_app_number] => 8/827861 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3550 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905993.pdf [firstpage_image] =>[orig_patent_app_number] => 827861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827861
Flash memory card with block memory address arrangement Apr 8, 1997 Issued
Array ( [id] => 3759113 [patent_doc_number] => 05787493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Control method and apparatus for direct execution of a program on an external apparatus using a randomly accessible and rewritable memory' [patent_app_type] => 1 [patent_app_number] => 8/841976 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6290 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787493.pdf [firstpage_image] =>[orig_patent_app_number] => 841976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841976
Control method and apparatus for direct execution of a program on an external apparatus using a randomly accessible and rewritable memory Apr 7, 1997 Issued
Array ( [id] => 3955521 [patent_doc_number] => 05940876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Stride instruction for fetching data separated by a stride amount' [patent_app_type] => 1 [patent_app_number] => 8/831195 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940876.pdf [firstpage_image] =>[orig_patent_app_number] => 831195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831195
Stride instruction for fetching data separated by a stride amount Apr 1, 1997 Issued
Array ( [id] => 4240182 [patent_doc_number] => 06012132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table' [patent_app_type] => 1 [patent_app_number] => 8/829782 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6207 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012132.pdf [firstpage_image] =>[orig_patent_app_number] => 829782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829782
Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table Mar 30, 1997 Issued
Array ( [id] => 3954666 [patent_doc_number] => 05873122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Memory system performing fast access to a memory location by omitting transfer of a redundant address' [patent_app_type] => 1 [patent_app_number] => 8/815600 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4945 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873122.pdf [firstpage_image] =>[orig_patent_app_number] => 815600 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/815600
Memory system performing fast access to a memory location by omitting transfer of a redundant address Mar 11, 1997 Issued
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