Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3782103 [patent_doc_number] => 05845324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access' [patent_app_type] => 1 [patent_app_number] => 8/815357 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12618 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845324.pdf [firstpage_image] =>[orig_patent_app_number] => 815357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/815357
Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access Mar 10, 1997 Issued
Array ( [id] => 4147671 [patent_doc_number] => 06128714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of processing a data move instruction for moving data between main storage and extended storage and data move instruction processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/813633 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14400 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128714.pdf [firstpage_image] =>[orig_patent_app_number] => 813633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813633
Method of processing a data move instruction for moving data between main storage and extended storage and data move instruction processing apparatus Mar 6, 1997 Issued
Array ( [id] => 4208680 [patent_doc_number] => 06154805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Realtime clock with page mode addressing' [patent_app_type] => 1 [patent_app_number] => 8/810130 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5810 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154805.pdf [firstpage_image] =>[orig_patent_app_number] => 810130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/810130
Realtime clock with page mode addressing Feb 24, 1997 Issued
Array ( [id] => 3954724 [patent_doc_number] => 05873125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Logical address structure for disk memories' [patent_app_type] => 1 [patent_app_number] => 8/801206 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 10686 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873125.pdf [firstpage_image] =>[orig_patent_app_number] => 801206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801206
Logical address structure for disk memories Feb 17, 1997 Issued
Array ( [id] => 3816042 [patent_doc_number] => 05829049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Simultaneous execution of two memory reference instructions with only one address calculation' [patent_app_type] => 1 [patent_app_number] => 8/785105 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3052 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829049.pdf [firstpage_image] =>[orig_patent_app_number] => 785105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785105
Simultaneous execution of two memory reference instructions with only one address calculation Jan 20, 1997 Issued
Array ( [id] => 3806137 [patent_doc_number] => 05822789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Video memory arrangement' [patent_app_type] => 1 [patent_app_number] => 8/779200 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9279 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822789.pdf [firstpage_image] =>[orig_patent_app_number] => 779200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779200
Video memory arrangement Jan 5, 1997 Issued
Array ( [id] => 3913575 [patent_doc_number] => 05835962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Parallel access micro-TLB to speed up address translation' [patent_app_type] => 1 [patent_app_number] => 8/772835 [patent_app_country] => US [patent_app_date] => 1996-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4507 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835962.pdf [firstpage_image] =>[orig_patent_app_number] => 772835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772835
Parallel access micro-TLB to speed up address translation Dec 23, 1996 Issued
Array ( [id] => 3808075 [patent_doc_number] => 05727178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'System and method for reducing stack physical memory requirements in a multitasking operating system' [patent_app_type] => 1 [patent_app_number] => 8/759450 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7090 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727178.pdf [firstpage_image] =>[orig_patent_app_number] => 759450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759450
System and method for reducing stack physical memory requirements in a multitasking operating system Dec 4, 1996 Issued
Array ( [id] => 3996111 [patent_doc_number] => 05918252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Apparatus and method for generating a modulo address' [patent_app_type] => 1 [patent_app_number] => 8/756268 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918252.pdf [firstpage_image] =>[orig_patent_app_number] => 756268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756268
Apparatus and method for generating a modulo address Nov 24, 1996 Issued
Array ( [id] => 3901149 [patent_doc_number] => 05897667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner' [patent_app_type] => 1 [patent_app_number] => 8/755246 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2290 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897667.pdf [firstpage_image] =>[orig_patent_app_number] => 755246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755246
Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner Nov 21, 1996 Issued
Array ( [id] => 3898432 [patent_doc_number] => 05765217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus to perform bus reflection operation using a data processor' [patent_app_type] => 1 [patent_app_number] => 8/749881 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6082 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765217.pdf [firstpage_image] =>[orig_patent_app_number] => 749881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/749881
Method and apparatus to perform bus reflection operation using a data processor Nov 14, 1996 Issued
Array ( [id] => 3806104 [patent_doc_number] => 05822787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Application binary interface and method of interfacing binary application program to digital computer including efficient acquistion of global offset table (GOT) absolute base address' [patent_app_type] => 1 [patent_app_number] => 8/744446 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 12456 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822787.pdf [firstpage_image] =>[orig_patent_app_number] => 744446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744446
Application binary interface and method of interfacing binary application program to digital computer including efficient acquistion of global offset table (GOT) absolute base address Nov 7, 1996 Issued
Array ( [id] => 4368133 [patent_doc_number] => 06276844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Clustered, buffered simms and assemblies thereof' [patent_app_type] => 1 [patent_app_number] => 8/744006 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 5991 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/276/06276844.pdf [firstpage_image] =>[orig_patent_app_number] => 744006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744006
Clustered, buffered simms and assemblies thereof Oct 29, 1996 Issued
Array ( [id] => 4057718 [patent_doc_number] => 05913050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method and apparatus for providing address-size backward compatibility in a processor using segmented memory' [patent_app_type] => 1 [patent_app_number] => 8/735048 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5320 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913050.pdf [firstpage_image] =>[orig_patent_app_number] => 735048 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735048
Method and apparatus for providing address-size backward compatibility in a processor using segmented memory Oct 21, 1996 Issued
Array ( [id] => 3745196 [patent_doc_number] => 05694566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Memory patching device' [patent_app_type] => 1 [patent_app_number] => 8/721385 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3244 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694566.pdf [firstpage_image] =>[orig_patent_app_number] => 721385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721385
Memory patching device Sep 25, 1996 Issued
Array ( [id] => 3907995 [patent_doc_number] => 05778415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Apparatus, systems and methods for controlling electronic memories' [patent_app_type] => 1 [patent_app_number] => 8/707897 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5265 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778415.pdf [firstpage_image] =>[orig_patent_app_number] => 707897 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707897
Apparatus, systems and methods for controlling electronic memories Sep 11, 1996 Issued
Array ( [id] => 3955492 [patent_doc_number] => 05940874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Memory device speed tester' [patent_app_type] => 1 [patent_app_number] => 8/700552 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2103 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940874.pdf [firstpage_image] =>[orig_patent_app_number] => 700552 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/700552
Memory device speed tester Aug 15, 1996 Issued
08/691229 COMPRESSION OF DATA IN READ ONLY STORAGE AND EMBEDDED SYSTEMS Jul 31, 1996 Abandoned
Array ( [id] => 3830647 [patent_doc_number] => 05832533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method and system for addressing registers in a data processing unit in an indexed addressing mode' [patent_app_type] => 1 [patent_app_number] => 8/687825 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4609 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832533.pdf [firstpage_image] =>[orig_patent_app_number] => 687825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687825
Method and system for addressing registers in a data processing unit in an indexed addressing mode Jul 25, 1996 Issued
Array ( [id] => 3833589 [patent_doc_number] => 05813045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Conditional early data address generation mechanism for a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/685653 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813045.pdf [firstpage_image] =>[orig_patent_app_number] => 685653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/685653
Conditional early data address generation mechanism for a microprocessor Jul 23, 1996 Issued
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