Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4001894 [patent_doc_number] => 05950232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Fetching apparatus for fetching data from a main memory' [patent_app_type] => 1 [patent_app_number] => 8/684622 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2201 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950232.pdf [firstpage_image] =>[orig_patent_app_number] => 684622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684622
Fetching apparatus for fetching data from a main memory Jul 21, 1996 Issued
Array ( [id] => 3898317 [patent_doc_number] => 05765209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages' [patent_app_type] => 1 [patent_app_number] => 8/699520 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5593 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765209.pdf [firstpage_image] =>[orig_patent_app_number] => 699520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699520
Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages Jul 17, 1996 Issued
Array ( [id] => 4126832 [patent_doc_number] => 06058464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Circuits, systems and method for address mapping' [patent_app_type] => 1 [patent_app_number] => 8/677125 [patent_app_country] => US [patent_app_date] => 1996-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5398 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058464.pdf [firstpage_image] =>[orig_patent_app_number] => 677125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677125
Circuits, systems and method for address mapping Jul 8, 1996 Issued
Array ( [id] => 3913638 [patent_doc_number] => 05835966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Semiconductor memory device and memory access system using a four-state address signal' [patent_app_type] => 1 [patent_app_number] => 8/674744 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 121 [patent_no_of_words] => 8740 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835966.pdf [firstpage_image] =>[orig_patent_app_number] => 674744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674744
Semiconductor memory device and memory access system using a four-state address signal Jul 1, 1996 Issued
Array ( [id] => 3967464 [patent_doc_number] => 05983332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture' [patent_app_type] => 1 [patent_app_number] => 8/672982 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6213 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983332.pdf [firstpage_image] =>[orig_patent_app_number] => 672982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672982
Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture Jun 30, 1996 Issued
Array ( [id] => 4370963 [patent_doc_number] => 06216197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for extending printer memory using a network file system' [patent_app_type] => 1 [patent_app_number] => 8/673125 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216197.pdf [firstpage_image] =>[orig_patent_app_number] => 673125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673125
Method and apparatus for extending printer memory using a network file system Jun 30, 1996 Issued
Array ( [id] => 3954970 [patent_doc_number] => 05900023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for removing power-of-two restrictions on distributed addressing' [patent_app_type] => 1 [patent_app_number] => 8/673436 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900023.pdf [firstpage_image] =>[orig_patent_app_number] => 673436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673436
Method and apparatus for removing power-of-two restrictions on distributed addressing Jun 27, 1996 Issued
Array ( [id] => 4059708 [patent_doc_number] => 05875473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Multi-processor system and method for controlling access to a page descriptor during the process of updating the page descriptors' [patent_app_type] => 1 [patent_app_number] => 8/671012 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875473.pdf [firstpage_image] =>[orig_patent_app_number] => 671012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671012
Multi-processor system and method for controlling access to a page descriptor during the process of updating the page descriptors Jun 27, 1996 Issued
Array ( [id] => 3947419 [patent_doc_number] => 05953747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Apparatus and method for serialized set prediction' [patent_app_type] => 1 [patent_app_number] => 8/668316 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5096 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953747.pdf [firstpage_image] =>[orig_patent_app_number] => 668316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668316
Apparatus and method for serialized set prediction Jun 25, 1996 Issued
Array ( [id] => 4092198 [patent_doc_number] => 05966721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Digital signal recording method and disk reproducing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/669245 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3192 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966721.pdf [firstpage_image] =>[orig_patent_app_number] => 669245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/669245
Digital signal recording method and disk reproducing apparatus Jun 23, 1996 Issued
Array ( [id] => 3765525 [patent_doc_number] => 05802574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for quickly modifying cache state' [patent_app_type] => 1 [patent_app_number] => 8/670753 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3734 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802574.pdf [firstpage_image] =>[orig_patent_app_number] => 670753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670753
Method and apparatus for quickly modifying cache state Jun 23, 1996 Issued
Array ( [id] => 4018636 [patent_doc_number] => 05924128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Pseudo zero cycle address generator and fast memory access' [patent_app_type] => 1 [patent_app_number] => 8/668262 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 9482 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924128.pdf [firstpage_image] =>[orig_patent_app_number] => 668262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668262
Pseudo zero cycle address generator and fast memory access Jun 19, 1996 Issued
Array ( [id] => 3812529 [patent_doc_number] => 05828821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Checkpoint restart method and apparatus utilizing multiple log memories' [patent_app_type] => 1 [patent_app_number] => 8/665542 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7025 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828821.pdf [firstpage_image] =>[orig_patent_app_number] => 665542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665542
Checkpoint restart method and apparatus utilizing multiple log memories Jun 17, 1996 Issued
Array ( [id] => 3907981 [patent_doc_number] => 05778414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Performance enhancing memory interleaver for data frame processing' [patent_app_type] => 1 [patent_app_number] => 8/663562 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9603 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778414.pdf [firstpage_image] =>[orig_patent_app_number] => 663562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663562
Performance enhancing memory interleaver for data frame processing Jun 12, 1996 Issued
Array ( [id] => 4059003 [patent_doc_number] => 05909696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Method and apparatus for caching system management mode information with other information' [patent_app_type] => 1 [patent_app_number] => 8/656922 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8509 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909696.pdf [firstpage_image] =>[orig_patent_app_number] => 656922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656922
Method and apparatus for caching system management mode information with other information Jun 3, 1996 Issued
Array ( [id] => 4019769 [patent_doc_number] => 05860113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'System for using a dirty bit with a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/660205 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11942 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860113.pdf [firstpage_image] =>[orig_patent_app_number] => 660205 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660205
System for using a dirty bit with a cache memory Jun 2, 1996 Issued
Array ( [id] => 3767148 [patent_doc_number] => 05721857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/651506 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11065 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721857.pdf [firstpage_image] =>[orig_patent_app_number] => 651506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651506
Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor May 21, 1996 Issued
Array ( [id] => 3798645 [patent_doc_number] => 05809562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Cache array select logic allowing cache array size to differ from physical page size' [patent_app_type] => 1 [patent_app_number] => 8/655306 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10033 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809562.pdf [firstpage_image] =>[orig_patent_app_number] => 655306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655306
Cache array select logic allowing cache array size to differ from physical page size May 19, 1996 Issued
Array ( [id] => 3765593 [patent_doc_number] => 05802579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'System and method for simultaneously reading and writing data in a random access memory' [patent_app_type] => 1 [patent_app_number] => 8/648792 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3150 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802579.pdf [firstpage_image] =>[orig_patent_app_number] => 648792 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648792
System and method for simultaneously reading and writing data in a random access memory May 15, 1996 Issued
Array ( [id] => 3750959 [patent_doc_number] => 05699539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Virtual memory management system and method using data compression' [patent_app_type] => 1 [patent_app_number] => 8/646059 [patent_app_country] => US [patent_app_date] => 1996-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 14423 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 580 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699539.pdf [firstpage_image] =>[orig_patent_app_number] => 646059 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/646059
Virtual memory management system and method using data compression May 6, 1996 Issued
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