
Than Vinh Nguyen
Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )
| Most Active Art Unit | 2138 |
| Art Unit(s) | 2188, 2138, 2187, 2787, 2759, 2309, 2751 |
| Total Applications | 1861 |
| Issued Applications | 1652 |
| Pending Applications | 79 |
| Abandoned Applications | 148 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3973443
[patent_doc_number] => 05978892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Virtual memory allocation in a virtual address space having an inaccessible gap'
[patent_app_type] => 1
[patent_app_number] => 8/642706
[patent_app_country] => US
[patent_app_date] => 1996-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 32
[patent_no_of_words] => 22732
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[pdf_file] => patents/05/978/05978892.pdf
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Array
(
[id] => 3967422
[patent_doc_number] => 05983329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Caching virtual memory locks'
[patent_app_type] => 1
[patent_app_number] => 8/643262
[patent_app_country] => US
[patent_app_date] => 1996-05-03
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/643262 | Caching virtual memory locks | May 2, 1996 | Issued |
Array
(
[id] => 4151890
[patent_doc_number] => 06035384
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[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Solid state disk drive address generator with multiplier circuit'
[patent_app_type] => 1
[patent_app_number] => 8/641934
[patent_app_country] => US
[patent_app_date] => 1996-05-02
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[patent_drawing_sheets_cnt] => 14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/641934 | Solid state disk drive address generator with multiplier circuit | May 1, 1996 | Issued |
Array
(
[id] => 3898086
[patent_doc_number] => 05765194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Timing consistent dynamic compare with force miss circuit'
[patent_app_type] => 1
[patent_app_number] => 8/641655
[patent_app_country] => US
[patent_app_date] => 1996-05-01
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[firstpage_image] =>[orig_patent_app_number] => 641655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/641655 | Timing consistent dynamic compare with force miss circuit | Apr 30, 1996 | Issued |
Array
(
[id] => 3888792
[patent_doc_number] => 05893929
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[patent_issue_date] => 1999-04-13
[patent_title] => 'Mutually controlled match-line-to-word-line transfer circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/639555 | Mutually controlled match-line-to-word-line transfer circuit | Apr 28, 1996 | Issued |
Array
(
[id] => 3870983
[patent_doc_number] => 05706461
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[patent_issue_date] => 1998-01-06
[patent_title] => 'Method and apparatus for implementing virtual memory having multiple selected page sizes'
[patent_app_type] => 1
[patent_app_number] => 8/638223
[patent_app_country] => US
[patent_app_date] => 1996-04-26
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[firstpage_image] =>[orig_patent_app_number] => 638223
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/638223 | Method and apparatus for implementing virtual memory having multiple selected page sizes | Apr 25, 1996 | Issued |
Array
(
[id] => 3765070
[patent_doc_number] => 05802543
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[patent_issue_date] => 1998-09-01
[patent_title] => 'Paging receiver employing memory banking system'
[patent_app_type] => 1
[patent_app_number] => 8/637492
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/637492 | Paging receiver employing memory banking system | Apr 24, 1996 | Issued |
Array
(
[id] => 4020048
[patent_doc_number] => 05860130
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[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets'
[patent_app_type] => 1
[patent_app_number] => 8/636579
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636579 | Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets | Apr 22, 1996 | Issued |
Array
(
[id] => 3759153
[patent_doc_number] => 05787496
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[patent_issue_date] => 1998-07-28
[patent_title] => 'Digital signal processor having a partitioned memory with first and second address areas for receiving and storing data in sychronism with first and second sampling clocks'
[patent_app_type] => 1
[patent_app_number] => 8/636342
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Array
(
[id] => 3843527
[patent_doc_number] => 05784707
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[patent_issue_date] => 1998-07-21
[patent_title] => 'Method and apparatus for managing virtual computer memory with multiple page sizes'
[patent_app_type] => 1
[patent_app_number] => 8/634956
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[patent_app_date] => 1996-04-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634956 | Method and apparatus for managing virtual computer memory with multiple page sizes | Apr 18, 1996 | Issued |
Array
(
[id] => 3900807
[patent_doc_number] => 05749084
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[patent_issue_date] => 1998-05-05
[patent_title] => 'Address generation unit with segmented addresses in a microprocessor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634092 | Address generation unit with segmented addresses in a microprocessor | Apr 16, 1996 | Issued |
Array
(
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[patent_title] => 'Microprocessor having address generation units for efficient generation of memory operation addresses'
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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