Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3973443 [patent_doc_number] => 05978892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Virtual memory allocation in a virtual address space having an inaccessible gap' [patent_app_type] => 1 [patent_app_number] => 8/642706 [patent_app_country] => US [patent_app_date] => 1996-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 22732 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978892.pdf [firstpage_image] =>[orig_patent_app_number] => 642706 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/642706
Virtual memory allocation in a virtual address space having an inaccessible gap May 2, 1996 Issued
Array ( [id] => 3967422 [patent_doc_number] => 05983329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Caching virtual memory locks' [patent_app_type] => 1 [patent_app_number] => 8/643262 [patent_app_country] => US [patent_app_date] => 1996-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7759 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983329.pdf [firstpage_image] =>[orig_patent_app_number] => 643262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643262
Caching virtual memory locks May 2, 1996 Issued
Array ( [id] => 4151890 [patent_doc_number] => 06035384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Solid state disk drive address generator with multiplier circuit' [patent_app_type] => 1 [patent_app_number] => 8/641934 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2782 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035384.pdf [firstpage_image] =>[orig_patent_app_number] => 641934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641934
Solid state disk drive address generator with multiplier circuit May 1, 1996 Issued
Array ( [id] => 3898086 [patent_doc_number] => 05765194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Timing consistent dynamic compare with force miss circuit' [patent_app_type] => 1 [patent_app_number] => 8/641655 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4063 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765194.pdf [firstpage_image] =>[orig_patent_app_number] => 641655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641655
Timing consistent dynamic compare with force miss circuit Apr 30, 1996 Issued
Array ( [id] => 3888792 [patent_doc_number] => 05893929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Mutually controlled match-line-to-word-line transfer circuit' [patent_app_type] => 1 [patent_app_number] => 8/639555 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893929.pdf [firstpage_image] =>[orig_patent_app_number] => 639555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639555
Mutually controlled match-line-to-word-line transfer circuit Apr 28, 1996 Issued
Array ( [id] => 3870983 [patent_doc_number] => 05706461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method and apparatus for implementing virtual memory having multiple selected page sizes' [patent_app_type] => 1 [patent_app_number] => 8/638223 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3700 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706461.pdf [firstpage_image] =>[orig_patent_app_number] => 638223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638223
Method and apparatus for implementing virtual memory having multiple selected page sizes Apr 25, 1996 Issued
Array ( [id] => 3765070 [patent_doc_number] => 05802543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Paging receiver employing memory banking system' [patent_app_type] => 1 [patent_app_number] => 8/637492 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3097 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802543.pdf [firstpage_image] =>[orig_patent_app_number] => 637492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637492
Paging receiver employing memory banking system Apr 24, 1996 Issued
Array ( [id] => 4020048 [patent_doc_number] => 05860130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets' [patent_app_type] => 1 [patent_app_number] => 8/636579 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 7864 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860130.pdf [firstpage_image] =>[orig_patent_app_number] => 636579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636579
Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets Apr 22, 1996 Issued
Array ( [id] => 3759153 [patent_doc_number] => 05787496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Digital signal processor having a partitioned memory with first and second address areas for receiving and storing data in sychronism with first and second sampling clocks' [patent_app_type] => 1 [patent_app_number] => 8/636342 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4143 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787496.pdf [firstpage_image] =>[orig_patent_app_number] => 636342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636342
Digital signal processor having a partitioned memory with first and second address areas for receiving and storing data in sychronism with first and second sampling clocks Apr 22, 1996 Issued
Array ( [id] => 3843527 [patent_doc_number] => 05784707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and apparatus for managing virtual computer memory with multiple page sizes' [patent_app_type] => 1 [patent_app_number] => 8/634956 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10591 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784707.pdf [firstpage_image] =>[orig_patent_app_number] => 634956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634956
Method and apparatus for managing virtual computer memory with multiple page sizes Apr 18, 1996 Issued
Array ( [id] => 3900807 [patent_doc_number] => 05749084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Address generation unit with segmented addresses in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/634092 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4793 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749084.pdf [firstpage_image] =>[orig_patent_app_number] => 634092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634092
Address generation unit with segmented addresses in a microprocessor Apr 16, 1996 Issued
Array ( [id] => 4195106 [patent_doc_number] => 06085302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Microprocessor having address generation units for efficient generation of memory operation addresses' [patent_app_type] => 1 [patent_app_number] => 8/633351 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085302.pdf [firstpage_image] =>[orig_patent_app_number] => 633351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633351
Microprocessor having address generation units for efficient generation of memory operation addresses Apr 16, 1996 Issued
Array ( [id] => 3913686 [patent_doc_number] => 05835968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Apparatus for providing memory and register operands concurrently to functional units' [patent_app_type] => 1 [patent_app_number] => 8/633302 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 16886 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835968.pdf [firstpage_image] =>[orig_patent_app_number] => 633302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633302
Apparatus for providing memory and register operands concurrently to functional units Apr 16, 1996 Issued
Array ( [id] => 3913024 [patent_doc_number] => 05835926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Multiple memory addressing using adjustable chip select' [patent_app_type] => 1 [patent_app_number] => 8/631039 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1296 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835926.pdf [firstpage_image] =>[orig_patent_app_number] => 631039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631039
Multiple memory addressing using adjustable chip select Apr 11, 1996 Issued
Array ( [id] => 3997372 [patent_doc_number] => 05911151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Optimizing block-sized operand movement utilizing standard instructions' [patent_app_type] => 1 [patent_app_number] => 8/630152 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911151.pdf [firstpage_image] =>[orig_patent_app_number] => 630152 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630152
Optimizing block-sized operand movement utilizing standard instructions Apr 9, 1996 Issued
Array ( [id] => 3978307 [patent_doc_number] => 05937435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'System and method for skip-sector mapping in a data recording disk drive' [patent_app_type] => 1 [patent_app_number] => 8/628304 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 14480 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937435.pdf [firstpage_image] =>[orig_patent_app_number] => 628304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/628304
System and method for skip-sector mapping in a data recording disk drive Apr 4, 1996 Issued
Array ( [id] => 3841981 [patent_doc_number] => 05732404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Flexible expansion of virtual memory addressing' [patent_app_type] => 1 [patent_app_number] => 8/625461 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14176 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732404.pdf [firstpage_image] =>[orig_patent_app_number] => 625461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625461
Flexible expansion of virtual memory addressing Mar 28, 1996 Issued
Array ( [id] => 4019287 [patent_doc_number] => 05860080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Multicasting system for selecting a group of memory devices for operation' [patent_app_type] => 1 [patent_app_number] => 8/618628 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860080.pdf [firstpage_image] =>[orig_patent_app_number] => 618628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618628
Multicasting system for selecting a group of memory devices for operation Mar 18, 1996 Issued
Array ( [id] => 3970625 [patent_doc_number] => 05991861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of enabling and disabling a data function in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/617991 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10678 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991861.pdf [firstpage_image] =>[orig_patent_app_number] => 617991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617991
Method of enabling and disabling a data function in an integrated circuit Mar 14, 1996 Issued
Array ( [id] => 4236523 [patent_doc_number] => 06041396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Segment descriptor cache addressed by part of the physical address of the desired descriptor' [patent_app_type] => 1 [patent_app_number] => 8/615912 [patent_app_country] => US [patent_app_date] => 1996-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041396.pdf [firstpage_image] =>[orig_patent_app_number] => 615912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615912
Segment descriptor cache addressed by part of the physical address of the desired descriptor Mar 13, 1996 Issued
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