Than Vinh Nguyen

Array ( [id] => 3758679 [patent_doc_number] => 05787462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'System and method for memory management in an array of heat producing devices to prevent local overheating' [patent_app_type] => 1 [patent_app_number] => 8/609202 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787462.pdf [firstpage_image] =>[orig_patent_app_number] => 609202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3730539 [patent_doc_number] => 05617552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Lossless data compression system and method' [patent_app_type] => 1 [patent_app_number] => 8/613433 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 14426 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617552.pdf [firstpage_image] =>[orig_patent_app_number] => 613433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160410 [patent_doc_number] => 06061759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Hidden precharge pseudo cache DRAM' [patent_app_type] => 1 [patent_app_number] => 8/599075 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5447 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061759.pdf [firstpage_image] =>[orig_patent_app_number] => 599075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3765951 [patent_doc_number] => 05802603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for asymmetric/symmetric DRAM detection' [patent_app_type] => 1 [patent_app_number] => 8/599056 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802603.pdf [firstpage_image] =>[orig_patent_app_number] => 599056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3751067 [patent_doc_number] => 05699545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Row address generator in a memory address system' [patent_app_type] => 1 [patent_app_number] => 8/596972 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2247 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699545.pdf [firstpage_image] =>[orig_patent_app_number] => 596972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4020120 [patent_doc_number] => 05860135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'File managing device of a non-volatile memory, a memory card and method for controlling a file system' [patent_app_type] => 1 [patent_app_number] => 8/587492 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4083 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860135.pdf [firstpage_image] =>[orig_patent_app_number] => 587492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025245 [patent_doc_number] => 06006314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Image processing system, storage device therefor and accessing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/587655 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006314.pdf [firstpage_image] =>[orig_patent_app_number] => 587655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3781872 [patent_doc_number] => 05845308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Wrapped-line cache for microprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/578102 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845308.pdf [firstpage_image] =>[orig_patent_app_number] => 578102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3759139 [patent_doc_number] => 05787495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method and apparatus for selector storing and restoration' [patent_app_type] => 1 [patent_app_number] => 8/572898 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3040 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787495.pdf [firstpage_image] =>[orig_patent_app_number] => 572898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3901121 [patent_doc_number] => 05897665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Register addressing for register-register architectures used for microprocessors and microcontrollers' [patent_app_type] => 1 [patent_app_number] => 8/573482 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897665.pdf [firstpage_image] =>[orig_patent_app_number] => 573482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3854511 [patent_doc_number] => 05708790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Virtual memory mapping method and system for address translation mapping of logical memory partitions for BAT and TLB entries in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/570957 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4870 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708790.pdf [firstpage_image] =>[orig_patent_app_number] => 570957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767166 [patent_doc_number] => 05721858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Virtual memory mapping method and system for memory management of pools of logical partitions for bat and TLB entries in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/571066 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721858.pdf [firstpage_image] =>[orig_patent_app_number] => 571066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3898099 [patent_doc_number] => 05765195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms' [patent_app_type] => 1 [patent_app_number] => 8/569542 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3952 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765195.pdf [firstpage_image] =>[orig_patent_app_number] => 569542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3913763 [patent_doc_number] => 05835971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and apparatus for generating addresses in parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 8/567232 [patent_app_country] => US [patent_app_date] => 1995-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12167 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835971.pdf [firstpage_image] =>[orig_patent_app_number] => 567232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853695 [patent_doc_number] => 05761740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method of and apparatus for rapidly loading addressing registers' [patent_app_type] => 1 [patent_app_number] => 8/566116 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8543 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761740.pdf [firstpage_image] =>[orig_patent_app_number] => 566116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3765925 [patent_doc_number] => 05802601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Interface between a memory having a given number of address inputs and a processor having fewer address outputs, and processor and memory equipped accordingly' [patent_app_type] => 1 [patent_app_number] => 8/561415 [patent_app_country] => US [patent_app_date] => 1995-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2110 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802601.pdf [firstpage_image] =>[orig_patent_app_number] => 561415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767182 [patent_doc_number] => 05721859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Counter control circuit in a burst memory' [patent_app_type] => 1 [patent_app_number] => 8/553156 [patent_app_country] => US [patent_app_date] => 1995-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8041 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721859.pdf [firstpage_image] =>[orig_patent_app_number] => 553156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767132 [patent_doc_number] => 05721856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Optical disk write method' [patent_app_type] => 1 [patent_app_number] => 8/551516 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11211 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721856.pdf [firstpage_image] =>[orig_patent_app_number] => 551516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4124113 [patent_doc_number] => 06101590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Virtual memory system with local and global virtual address translation' [patent_app_type] => 1 [patent_app_number] => 8/541416 [patent_app_country] => US [patent_app_date] => 1995-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101590.pdf [firstpage_image] =>[orig_patent_app_number] => 541416 [rel_patent_id] =>[rel_patent_doc_number] =>)