Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3621237 [patent_doc_number] => 05590301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Address transformation in a cluster computer system' [patent_app_type] => 1 [patent_app_number] => 8/540106 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5713 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590301.pdf [firstpage_image] =>[orig_patent_app_number] => 540106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540106
Address transformation in a cluster computer system Oct 5, 1995 Issued
Array ( [id] => 4020163 [patent_doc_number] => 05860138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Processor with compiler-allocated, variable length intermediate storage' [patent_app_type] => 1 [patent_app_number] => 8/537556 [patent_app_country] => US [patent_app_date] => 1995-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6412 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860138.pdf [firstpage_image] =>[orig_patent_app_number] => 537556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537556
Processor with compiler-allocated, variable length intermediate storage Oct 1, 1995 Issued
Array ( [id] => 3751039 [patent_doc_number] => 05699543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Profile guided TLB and cache optimization' [patent_app_type] => 1 [patent_app_number] => 8/536951 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2411 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699543.pdf [firstpage_image] =>[orig_patent_app_number] => 536951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536951
Profile guided TLB and cache optimization Sep 28, 1995 Issued
08/535395 MULTI-PORT MULTIPLE-SIMULTANEOUS-ACCESS DRAM CHIP Sep 27, 1995 Abandoned
Array ( [id] => 3700209 [patent_doc_number] => 05696925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Memory management unit with address translation function' [patent_app_type] => 1 [patent_app_number] => 8/525881 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6267 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696925.pdf [firstpage_image] =>[orig_patent_app_number] => 525881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525881
Memory management unit with address translation function Sep 7, 1995 Issued
Array ( [id] => 3852974 [patent_doc_number] => 05761693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus for enabling access to two contiguous addresses in units of a memory segment simultaneously' [patent_app_type] => 1 [patent_app_number] => 8/525146 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2050 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761693.pdf [firstpage_image] =>[orig_patent_app_number] => 525146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525146
Method and apparatus for enabling access to two contiguous addresses in units of a memory segment simultaneously Sep 7, 1995 Issued
Array ( [id] => 3894112 [patent_doc_number] => 05764944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for TLB invalidation mechanism for protective page fault' [patent_app_type] => 1 [patent_app_number] => 8/525021 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1939 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764944.pdf [firstpage_image] =>[orig_patent_app_number] => 525021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525021
Method and apparatus for TLB invalidation mechanism for protective page fault Sep 7, 1995 Issued
Array ( [id] => 3898397 [patent_doc_number] => 05765215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and system for efficient rename buffer deallocation within a processor' [patent_app_type] => 1 [patent_app_number] => 8/519556 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2977 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765215.pdf [firstpage_image] =>[orig_patent_app_number] => 519556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519556
Method and system for efficient rename buffer deallocation within a processor Aug 24, 1995 Issued
08/518426 SYSTEM AND METHOD FOR REDUCING STACK PHYSICAL MEMORY REQUIREMENTS IN A MULTITASKING OPERATING SYSTEM Aug 22, 1995 Abandoned
Array ( [id] => 3913699 [patent_doc_number] => 05835969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Address test pattern generator for burst transfer operation of a SDRAM' [patent_app_type] => 1 [patent_app_number] => 8/517271 [patent_app_country] => US [patent_app_date] => 1995-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3677 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835969.pdf [firstpage_image] =>[orig_patent_app_number] => 517271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517271
Address test pattern generator for burst transfer operation of a SDRAM Aug 21, 1995 Issued
08/510485 VIDEO MEMORY ARRANGEMENT Aug 1, 1995 Abandoned
Array ( [id] => 3898180 [patent_doc_number] => 05765201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Changing page size in storage media of computer system' [patent_app_type] => 1 [patent_app_number] => 8/509486 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3618 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765201.pdf [firstpage_image] =>[orig_patent_app_number] => 509486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509486
Changing page size in storage media of computer system Jul 30, 1995 Issued
Array ( [id] => 3900821 [patent_doc_number] => 05749085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Electronic memory addressing device especially for a memory organized into banks' [patent_app_type] => 1 [patent_app_number] => 8/492591 [patent_app_country] => US [patent_app_date] => 1995-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7191 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 493 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749085.pdf [firstpage_image] =>[orig_patent_app_number] => 492591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/492591
Electronic memory addressing device especially for a memory organized into banks Jun 19, 1995 Issued
08/457729 MEMORY ARRAY BASED DATA REORGANIZER Jun 11, 1995 Abandoned
Array ( [id] => 4255168 [patent_doc_number] => 06119213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for addressing data having variable data width using a fixed number of bits for address and width defining fields' [patent_app_type] => 1 [patent_app_number] => 8/484456 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 158 [patent_figures_cnt] => 132 [patent_no_of_words] => 77549 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119213.pdf [firstpage_image] =>[orig_patent_app_number] => 484456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484456
Method for addressing data having variable data width using a fixed number of bits for address and width defining fields Jun 6, 1995 Issued
Array ( [id] => 3700175 [patent_doc_number] => 05696923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register' [patent_app_type] => 1 [patent_app_number] => 8/474863 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 89 [patent_no_of_words] => 35661 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696923.pdf [firstpage_image] =>[orig_patent_app_number] => 474863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474863
Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register Jun 6, 1995 Issued
Array ( [id] => 4209025 [patent_doc_number] => 06154824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Multifunctional access devices, systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/474866 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 88 [patent_no_of_words] => 35376 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154824.pdf [firstpage_image] =>[orig_patent_app_number] => 474866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474866
Multifunctional access devices, systems and methods Jun 6, 1995 Issued
Array ( [id] => 3556241 [patent_doc_number] => 05555387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method and apparatus for implementing virtual memory having multiple selected page sizes' [patent_app_type] => 1 [patent_app_number] => 8/467266 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3698 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555387.pdf [firstpage_image] =>[orig_patent_app_number] => 467266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/467266
Method and apparatus for implementing virtual memory having multiple selected page sizes Jun 5, 1995 Issued
Array ( [id] => 4061158 [patent_doc_number] => 05895503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Address translation method and mechanism using physical address information including during a segmentation process' [patent_app_type] => 1 [patent_app_number] => 8/458479 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7197 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895503.pdf [firstpage_image] =>[orig_patent_app_number] => 458479 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/458479
Address translation method and mechanism using physical address information including during a segmentation process Jun 1, 1995 Issued
Array ( [id] => 4192382 [patent_doc_number] => 06141722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method and apparatus for reclaiming memory' [patent_app_type] => 1 [patent_app_number] => 8/457403 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6122 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141722.pdf [firstpage_image] =>[orig_patent_app_number] => 457403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/457403
Method and apparatus for reclaiming memory May 30, 1995 Issued
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