| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3662534
[patent_doc_number] => 05684975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Method for use in translating virtual addresses into absolute addresses'
[patent_app_type] => 1
[patent_app_number] => 8/453140
[patent_app_country] => US
[patent_app_date] => 1995-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6636
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684975.pdf
[firstpage_image] =>[orig_patent_app_number] => 453140
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/453140 | Method for use in translating virtual addresses into absolute addresses | May 29, 1995 | Issued |
Array
(
[id] => 3701102
[patent_doc_number] => 05692146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Method of implementing fast 486TM microprocessor compatible string operations'
[patent_app_type] => 1
[patent_app_number] => 8/451742
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 6294
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/692/05692146.pdf
[firstpage_image] =>[orig_patent_app_number] => 451742
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451742 | Method of implementing fast 486TM microprocessor compatible string operations | May 25, 1995 | Issued |
| 08/443368 | MEMORY CIRCUIT WITH BUILT-IN CACHE MEMORY | May 16, 1995 | Abandoned |
Array
(
[id] => 3681665
[patent_doc_number] => 05600812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Variable-length-code decoders storing decoding results and corresponding code-bit-length information in memory'
[patent_app_type] => 1
[patent_app_number] => 8/434006
[patent_app_country] => US
[patent_app_date] => 1995-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11981
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 577
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600812.pdf
[firstpage_image] =>[orig_patent_app_number] => 434006
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434006 | Variable-length-code decoders storing decoding results and corresponding code-bit-length information in memory | May 2, 1995 | Issued |
| 08/431367 | DUAL BUS NETWORK CACHE CONTROLLER SYSTEM | Apr 27, 1995 | Abandoned |
| 08/423005 | PARALLEL MEMORY DEVICE FOR IMAGE PROCESSING UTILIZING LINEAR TRANSFORMATION | Apr 13, 1995 | Abandoned |
Array
(
[id] => 1452254
[patent_doc_number] => 06370610
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Apparatus for swapping input values into corresponding output values'
[patent_app_type] => B1
[patent_app_number] => 08/421338
[patent_app_country] => US
[patent_app_date] => 1995-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4824
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/370/06370610.pdf
[firstpage_image] =>[orig_patent_app_number] => 08421338
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/421338 | Apparatus for swapping input values into corresponding output values | Apr 12, 1995 | Issued |
| 08/420539 | DATA PROCESSOR | Apr 11, 1995 | Abandoned |
Array
(
[id] => 3673023
[patent_doc_number] => 05649140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'System for use in translating virtual addresses into absolute addresses'
[patent_app_type] => 1
[patent_app_number] => 8/414671
[patent_app_country] => US
[patent_app_date] => 1995-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6650
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/649/05649140.pdf
[firstpage_image] =>[orig_patent_app_number] => 414671
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/414671 | System for use in translating virtual addresses into absolute addresses | Mar 30, 1995 | Issued |
Array
(
[id] => 3673108
[patent_doc_number] => 05649146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Modulo addressing buffer'
[patent_app_type] => 1
[patent_app_number] => 8/413709
[patent_app_country] => US
[patent_app_date] => 1995-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 5616
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/649/05649146.pdf
[firstpage_image] =>[orig_patent_app_number] => 413709
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/413709 | Modulo addressing buffer | Mar 29, 1995 | Issued |
Array
(
[id] => 4017486
[patent_doc_number] => 05859960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Semiconductor disk apparatus having a semiconductor memory for a recording medium'
[patent_app_type] => 1
[patent_app_number] => 8/408911
[patent_app_country] => US
[patent_app_date] => 1995-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 60
[patent_no_of_words] => 19135
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/859/05859960.pdf
[firstpage_image] =>[orig_patent_app_number] => 408911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/408911 | Semiconductor disk apparatus having a semiconductor memory for a recording medium | Mar 21, 1995 | Issued |
Array
(
[id] => 3751012
[patent_doc_number] => 05699541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Memory system using schottky diodes to reduce load capacitance'
[patent_app_type] => 1
[patent_app_number] => 8/406147
[patent_app_country] => US
[patent_app_date] => 1995-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 59
[patent_no_of_words] => 6152
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/699/05699541.pdf
[firstpage_image] =>[orig_patent_app_number] => 406147
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/406147 | Memory system using schottky diodes to reduce load capacitance | Mar 19, 1995 | Issued |
Array
(
[id] => 4371014
[patent_doc_number] => 06216200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Address queue'
[patent_app_type] => 1
[patent_app_number] => 8/404625
[patent_app_country] => US
[patent_app_date] => 1995-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 26044
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/216/06216200.pdf
[firstpage_image] =>[orig_patent_app_number] => 404625
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/404625 | Address queue | Mar 13, 1995 | Issued |
| 08/403227 | DISK CONTROLLING METHOD AND DISK CONTROLLING APPARATUS | Mar 12, 1995 | Abandoned |
Array
(
[id] => 3662521
[patent_doc_number] => 05684974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Method and apparatus for controlling reconfiguration of storage-device memory areas'
[patent_app_type] => 1
[patent_app_number] => 8/402371
[patent_app_country] => US
[patent_app_date] => 1995-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 8223
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684974.pdf
[firstpage_image] =>[orig_patent_app_number] => 402371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402371 | Method and apparatus for controlling reconfiguration of storage-device memory areas | Mar 12, 1995 | Issued |
| 08/397810 | PARALLEL ACCESS MIRCRO-TLB TO SPEED UP ADDRESS TRANSLATION | Mar 2, 1995 | Abandoned |
Array
(
[id] => 3860283
[patent_doc_number] => 05848438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Memory mapping defect management technique for automatic track processing without ID field'
[patent_app_type] => 1
[patent_app_number] => 8/399095
[patent_app_country] => US
[patent_app_date] => 1995-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 13275
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848438.pdf
[firstpage_image] =>[orig_patent_app_number] => 399095
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/399095 | Memory mapping defect management technique for automatic track processing without ID field | Mar 2, 1995 | Issued |
| 08/396939 | METHOD AND APPARATUS TO PERFORM BUS REFLECTION OPERATION USING A DATA PROCESSOR | Feb 28, 1995 | Abandoned |
Array
(
[id] => 3694540
[patent_doc_number] => 05634036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Method and apparatus for protecting memory with variable visibility of segment descriptor tables'
[patent_app_type] => 1
[patent_app_number] => 8/394843
[patent_app_country] => US
[patent_app_date] => 1995-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 2975
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/634/05634036.pdf
[firstpage_image] =>[orig_patent_app_number] => 394843
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/394843 | Method and apparatus for protecting memory with variable visibility of segment descriptor tables | Feb 26, 1995 | Issued |
Array
(
[id] => 3810237
[patent_doc_number] => 05842225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Method and apparatus for implementing non-faulting load instruction'
[patent_app_type] => 1
[patent_app_number] => 8/395579
[patent_app_country] => US
[patent_app_date] => 1995-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5405
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/842/05842225.pdf
[firstpage_image] =>[orig_patent_app_number] => 395579
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/395579 | Method and apparatus for implementing non-faulting load instruction | Feb 26, 1995 | Issued |