Thanh V. Pham

Array ( [id] => 10936618 [patent_doc_number] => 20140339639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES' [patent_app_type] => utility [patent_app_number] => 13/897568 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9171704 [patent_doc_number] => 20130313689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/897613 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9171621 [patent_doc_number] => 20130313606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'ILLUMINATING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/897212 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936629 [patent_doc_number] => 20140339650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION' [patent_app_type] => utility [patent_app_number] => 13/897112 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9817579 [patent_doc_number] => 08927363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Integrating channel SiGe into pFET structures' [patent_app_type] => utility [patent_app_number] => 13/896968 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5698 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936621 [patent_doc_number] => 20140339642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'REDUCTION OF OXIDE RECESSES FOR GATE HEIGHT CONTROL' [patent_app_type] => utility [patent_app_number] => 13/896807 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3792 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936629 [patent_doc_number] => 20140339650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION' [patent_app_type] => utility [patent_app_number] => 13/897112 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936629 [patent_doc_number] => 20140339650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION' [patent_app_type] => utility [patent_app_number] => 13/897112 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936629 [patent_doc_number] => 20140339650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION' [patent_app_type] => utility [patent_app_number] => 13/897112 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9557710 [patent_doc_number] => 20140175423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/896045 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936474 [patent_doc_number] => 20140339496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'Vertical Light Emitting Diode (VLED) Dice Having Confinement Layers With Roughened Surfaces And Methods Of Fabrication' [patent_app_type] => utility [patent_app_number] => 13/895421 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10838477 [patent_doc_number] => 08866156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Silicon carbide semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 13/895848 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5631 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9828107 [patent_doc_number] => 08937336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Passivation of group III-nitride heterojunction devices' [patent_app_type] => utility [patent_app_number] => 13/895511 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6767 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9951691 [patent_doc_number] => 09000483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Semiconductor device with fin structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 13/895367 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9178415 [patent_doc_number] => 20130320400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/895228 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5493 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10936590 [patent_doc_number] => 20140339611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS' [patent_app_type] => utility [patent_app_number] => 13/893896 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9994 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9996524 [patent_doc_number] => 09041127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'FinFET device technology with LDMOS structures for high voltage operations' [patent_app_type] => utility [patent_app_number] => 13/893466 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9233293 [patent_doc_number] => 08598601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Light emitting package' [patent_app_type] => utility [patent_app_number] => 13/892814 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13892814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9255125 [patent_doc_number] => 08618542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Response and header circuitry with command and frame marker inputs' [patent_app_type] => utility [patent_app_number] => 13/870319 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9678 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9245208 [patent_doc_number] => 08609488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith' [patent_app_type] => utility [patent_app_number] => 13/869112 [patent_app_country] => US [patent_app_date] => 2013-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869112 [rel_patent_id] =>[rel_patent_doc_number] =>)