Thanh V. Pham

Array ( [id] => 8838895 [patent_doc_number] => 20130134523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS' [patent_app_type] => utility [patent_app_number] => 13/752388 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2697 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8947787 [patent_doc_number] => 20130193567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'LEAD FRAME AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/751609 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9631953 [patent_doc_number] => 20140210061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'CHIP ARRANGEMENT AND CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/751207 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9631954 [patent_doc_number] => 20140210062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces' [patent_app_type] => utility [patent_app_number] => 13/751972 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5106 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9079164 [patent_doc_number] => 20130264694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'ELECTRONIC PACKAGE STRUCTURE HAVING EXPOSED LANDS AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/750532 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10093145 [patent_doc_number] => 09129975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Method of forming a thin substrate chip scale package device and structure' [patent_app_type] => utility [patent_app_number] => 13/750022 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 2803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8960883 [patent_doc_number] => 20130200485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/746532 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2885 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9530642 [patent_doc_number] => 08754518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-17 [patent_title] => 'Devices and methods for configuring conductive elements for a semiconductor package' [patent_app_type] => utility [patent_app_number] => 13/746874 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3833 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9552115 [patent_doc_number] => 08759163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Layout of a MOS array edge with density gradient smoothing' [patent_app_type] => utility [patent_app_number] => 13/744532 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13744532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9552903 [patent_doc_number] => 08759955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Semiconductor device with chips on isolated mount regions' [patent_app_type] => utility [patent_app_number] => 13/745330 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4053 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13745330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10502487 [patent_doc_number] => 09230889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic' [patent_app_type] => utility [patent_app_number] => 13/742426 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4881 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9600845 [patent_doc_number] => 20140197527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 13/742455 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7089 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9552848 [patent_doc_number] => 08759899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'Integration of 3D stacked IC device with peripheral circuits' [patent_app_type] => utility [patent_app_number] => 13/739914 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7962 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10882365 [patent_doc_number] => 08906743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods' [patent_app_type] => utility [patent_app_number] => 13/739331 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5644 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9594704 [patent_doc_number] => 20140191381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'INTEGRATED CIRCUIT MODULE WITH DUAL LEADFRAME' [patent_app_type] => utility [patent_app_number] => 13/737697 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2430 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9692529 [patent_doc_number] => 08823132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Two-portion shallow-trench isolation' [patent_app_type] => utility [patent_app_number] => 13/736082 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3490 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9446356 [patent_doc_number] => 20140117524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/735603 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3662 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8764914 [patent_doc_number] => 20130092951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/693048 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1203 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9971725 [patent_doc_number] => 09018740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Sensor with field effect transistor having the gate dielectric consisting of a layer of lipids and method of fabricating this transistor' [patent_app_type] => utility [patent_app_number] => 14/361026 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2609 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14361026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597532 [patent_doc_number] => 09318629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Method for fabricating sensor using multiple patterning processes' [patent_app_type] => utility [patent_app_number] => 14/125444 [patent_app_country] => US [patent_app_date] => 2012-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14125444 [rel_patent_id] =>[rel_patent_doc_number] =>)