Search

Thanh Y. Tran

Examiner (ID: 18218)

Most Active Art Unit
2817
Art Unit(s)
2822, 2827, 2892, 2817, 2841, 2829
Total Applications
1625
Issued Applications
1324
Pending Applications
127
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18183998 [patent_doc_number] => 20230044728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/968775 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968775
Stacked semiconductor dies for semiconductor device assemblies Oct 17, 2022 Issued
Array ( [id] => 18326630 [patent_doc_number] => 20230124758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => STACKED SEMICONDUCTOR ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/966205 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/966205
STACKED SEMICONDUCTOR ASSEMBLY Oct 13, 2022 Pending
Array ( [id] => 18326630 [patent_doc_number] => 20230124758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => STACKED SEMICONDUCTOR ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/966205 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/966205
STACKED SEMICONDUCTOR ASSEMBLY Oct 13, 2022 Pending
Array ( [id] => 18163540 [patent_doc_number] => 20230030133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/963959 [patent_app_country] => US [patent_app_date] => 2022-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/963959
Semiconductor device package Oct 10, 2022 Issued
Array ( [id] => 19356903 [patent_doc_number] => 12057359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/884499 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884499
Semiconductor package and method of fabricating the same Aug 8, 2022 Issued
Array ( [id] => 18024398 [patent_doc_number] => 20220375897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES [patent_app_type] => utility [patent_app_number] => 17/881998 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881998
Semiconductor device assemblies including multiple stacks of different semiconductor dies Aug 4, 2022 Issued
Array ( [id] => 18767000 [patent_doc_number] => 11817410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 17/876159 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876159 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876159
Integrated circuit package and method Jul 27, 2022 Issued
Array ( [id] => 17993409 [patent_doc_number] => 20220359446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/872000 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872000
Package structure and method of manufacturing the same Jul 24, 2022 Issued
Array ( [id] => 19138079 [patent_doc_number] => 11973055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/869977 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869977
Wafer bonding method Jul 20, 2022 Issued
Array ( [id] => 19138079 [patent_doc_number] => 11973055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/869977 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869977
Wafer bonding method Jul 20, 2022 Issued
Array ( [id] => 19138079 [patent_doc_number] => 11973055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/869977 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869977
Wafer bonding method Jul 20, 2022 Issued
Array ( [id] => 17993449 [patent_doc_number] => 20220359486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => 3D Semiconductor Package Including Memory Array [patent_app_type] => utility [patent_app_number] => 17/814194 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814194
3D semiconductor package including memory array Jul 20, 2022 Issued
Array ( [id] => 19138079 [patent_doc_number] => 11973055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Wafer bonding method [patent_app_type] => utility [patent_app_number] => 17/869977 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869977
Wafer bonding method Jul 20, 2022 Issued
Array ( [id] => 20111567 [patent_doc_number] => 12362303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/813812 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813812
Semiconductor memory device Jul 19, 2022 Issued
Array ( [id] => 20111567 [patent_doc_number] => 12362303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/813812 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813812
Semiconductor memory device Jul 19, 2022 Issued
Array ( [id] => 17986013 [patent_doc_number] => 20220352050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/866866 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866866 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866866
Semiconductor package Jul 17, 2022 Issued
Array ( [id] => 18228670 [patent_doc_number] => 20230067664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/865399 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865399
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jul 14, 2022 Pending
Array ( [id] => 18570619 [patent_doc_number] => 20230260956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING JOINT PORTION BETWEEN CONDUCTIVE CONNECTION STRUCTURES AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/864092 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864092
SEMICONDUCTOR DEVICE INCLUDING JOINT PORTION BETWEEN CONDUCTIVE CONNECTION STRUCTURES AND METHOD OF FABRICATING THE SAME Jul 12, 2022 Pending
Array ( [id] => 19552905 [patent_doc_number] => 12136618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Three-dimensional memory device with backside source contact [patent_app_type] => utility [patent_app_number] => 17/858695 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 12446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858695
Three-dimensional memory device with backside source contact Jul 5, 2022 Issued
Array ( [id] => 17986084 [patent_doc_number] => 20220352121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SEMICONDUCTOR PACKAGE HAVING PASSIVE SUPPORT WAFER [patent_app_type] => utility [patent_app_number] => 17/858031 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858031
SEMICONDUCTOR PACKAGE HAVING PASSIVE SUPPORT WAFER Jul 4, 2022 Pending
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