Search

Thanh Y. Tran

Examiner (ID: 18218)

Most Active Art Unit
2817
Art Unit(s)
2822, 2827, 2892, 2817, 2841, 2829
Total Applications
1625
Issued Applications
1324
Pending Applications
127
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19239505 [patent_doc_number] => 20240196701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DISPLAY DEVICE AND MOBILE TERMINAL [patent_app_type] => utility [patent_app_number] => 17/798966 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/798966
Display device and mobile terminal Jun 29, 2022 Issued
Array ( [id] => 20244243 [patent_doc_number] => 12424575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Three-dimensional semiconductor device [patent_app_type] => utility [patent_app_number] => 17/855241 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855241
Three-dimensional semiconductor device Jun 29, 2022 Issued
Array ( [id] => 20244243 [patent_doc_number] => 12424575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Three-dimensional semiconductor device [patent_app_type] => utility [patent_app_number] => 17/855241 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855241
Three-dimensional semiconductor device Jun 29, 2022 Issued
Array ( [id] => 18177634 [patent_doc_number] => 20230038363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING [patent_app_type] => utility [patent_app_number] => 17/848844 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848844
THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING Jun 23, 2022 Pending
Array ( [id] => 18967508 [patent_doc_number] => 11901289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor device structure with resistive element [patent_app_type] => utility [patent_app_number] => 17/848146 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848146
Semiconductor device structure with resistive element Jun 22, 2022 Issued
Array ( [id] => 18865999 [patent_doc_number] => 20230420436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING [patent_app_type] => utility [patent_app_number] => 17/846109 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846109
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING Jun 21, 2022 Pending
Array ( [id] => 18848944 [patent_doc_number] => 20230411348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => CHIP-FIRST LAYERED PACKAGING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/842093 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842093
CHIP-FIRST LAYERED PACKAGING ARCHITECTURE Jun 15, 2022 Pending
Array ( [id] => 17900966 [patent_doc_number] => 20220310628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/838555 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838555
Semiconductor device and driving method of semiconductor device Jun 12, 2022 Issued
Array ( [id] => 18833867 [patent_doc_number] => 20230402394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => THREE DIMENSIONAL (3D) MEMORY DEVICE AND FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 17/838964 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838964
Three dimensional (3D) memory device and fabrication method Jun 12, 2022 Issued
Array ( [id] => 20080916 [patent_doc_number] => 12354994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Three-dimensional memory device and fabrication method [patent_app_type] => utility [patent_app_number] => 17/838910 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 2460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838910
Three-dimensional memory device and fabrication method Jun 12, 2022 Issued
Array ( [id] => 18821125 [patent_doc_number] => 20230395466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => HIGH BANDWIDTH PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/831040 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831040
High bandwidth package structure Jun 1, 2022 Issued
Array ( [id] => 18821204 [patent_doc_number] => 20230395545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MODULAR CONSTRUCTION OF HYBRID-BONDED SEMICONDUCTOR DIE ASSEMBLIES AND RELATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/830224 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830224
Modular construction of hybrid-bonded semiconductor die assemblies and related systems and methods May 31, 2022 Issued
Array ( [id] => 18704735 [patent_doc_number] => 11791252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Package-on-package semiconductor assemblies and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/830022 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3415 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830022
Package-on-package semiconductor assemblies and methods of manufacturing the same May 31, 2022 Issued
Array ( [id] => 17870796 [patent_doc_number] => 20220293533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION [patent_app_type] => utility [patent_app_number] => 17/830250 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830250
Methods for forming three-dimensional memory devices with supporting structure for staircase region May 31, 2022 Issued
Array ( [id] => 19900264 [patent_doc_number] => 12278201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Non-volatile memory device with a conductive etch stop layer, method of manufacturing the same, and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/825076 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 10040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825076
Non-volatile memory device with a conductive etch stop layer, method of manufacturing the same, and memory system including the same May 25, 2022 Issued
Array ( [id] => 18812718 [patent_doc_number] => 20230387055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/804247 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804247
Microelectronic devices, related electronic systems, and methods of forming microelectronic devices May 25, 2022 Issued
Array ( [id] => 18124798 [patent_doc_number] => 20230010411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/752369 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752369
DISPLAY DEVICE May 23, 2022 Issued
Array ( [id] => 17840930 [patent_doc_number] => 20220278236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/744812 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744812
Semiconductor device May 15, 2022 Issued
Array ( [id] => 20389348 [patent_doc_number] => 12489083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => 3D laminated chip, and semiconductor package including the 3D laminated chip [patent_app_type] => utility [patent_app_number] => 17/743819 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743819
3D laminated chip, and semiconductor package including the 3D laminated chip May 12, 2022 Issued
Array ( [id] => 17833710 [patent_doc_number] => 20220271014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/742371 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742371
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF May 10, 2022 Pending
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