Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18236146 [patent_doc_number] => 11600714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/229617 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5494 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229617
Manufacturing method of semiconductor device Apr 12, 2021 Issued
Array ( [id] => 16981418 [patent_doc_number] => 20210225655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Methods For Depositing Fluorine/Carbon-Free Conformal Tungsten [patent_app_type] => utility [patent_app_number] => 17/223506 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223506
Methods for depositing fluorine/carbon-free conformal tungsten Apr 5, 2021 Issued
Array ( [id] => 18857544 [patent_doc_number] => 11855141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Local epitaxy nanofilms for nanowire stack GAA device [patent_app_type] => utility [patent_app_number] => 17/223273 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223273
Local epitaxy nanofilms for nanowire stack GAA device Apr 5, 2021 Issued
Array ( [id] => 19064654 [patent_doc_number] => 11943931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Non-volatile memory device with vertical state transistor and vertical selection transistor [patent_app_type] => utility [patent_app_number] => 17/220286 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220286 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220286
Non-volatile memory device with vertical state transistor and vertical selection transistor Mar 31, 2021 Issued
Array ( [id] => 18294044 [patent_doc_number] => 20230103730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SOLID-STATE IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 17/909822 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17909822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/909822
Solid-state imaging device Mar 16, 2021 Issued
Array ( [id] => 18317549 [patent_doc_number] => 11631633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Substrate structure, semiconductor package structure and method for manufacturing semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/204833 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 5399 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204833
Substrate structure, semiconductor package structure and method for manufacturing semiconductor package structure Mar 16, 2021 Issued
Array ( [id] => 19928417 [patent_doc_number] => 12302731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/201375 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201375
Display device Mar 14, 2021 Issued
Array ( [id] => 16936593 [patent_doc_number] => 20210202482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATING SUCH DEVICES [patent_app_type] => utility [patent_app_number] => 17/197496 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197496
Integrated circuit devices and methods of fabricating such devices Mar 9, 2021 Issued
Array ( [id] => 17262680 [patent_doc_number] => 20210375665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/197995 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197995
Semiconductor device and manufacturing method thereof Mar 9, 2021 Issued
Array ( [id] => 19199075 [patent_doc_number] => 11996324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Conductive feature of a semiconductor device and method of forming same [patent_app_type] => utility [patent_app_number] => 17/193201 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193201
Conductive feature of a semiconductor device and method of forming same Mar 4, 2021 Issued
Array ( [id] => 19494261 [patent_doc_number] => 12112984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Contact features of semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/192600 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192600
Contact features of semiconductor devices Mar 3, 2021 Issued
Array ( [id] => 17055771 [patent_doc_number] => 20210265205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DIELECTRIC ETCH STOP LAYER FOR REACTIVE ION ETCH (RIE) LAG REDUCTION AND CHAMFER CORNER PROTECTION [patent_app_type] => utility [patent_app_number] => 17/179117 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179117
DIELECTRIC ETCH STOP LAYER FOR REACTIVE ION ETCH (RIE) LAG REDUCTION AND CHAMFER CORNER PROTECTION Feb 17, 2021 Abandoned
Array ( [id] => 18230416 [patent_doc_number] => 20230069410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => HIGH RESOLUTION MONOLITHIC RGB ARRAYS [patent_app_type] => utility [patent_app_number] => 17/799685 [patent_app_country] => US [patent_app_date] => 2021-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/799685
HIGH RESOLUTION MONOLITHIC RGB ARRAYS Feb 14, 2021 Pending
Array ( [id] => 16904940 [patent_doc_number] => 20210183856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS [patent_app_type] => utility [patent_app_number] => 17/175340 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175340
Minimizing shorting between FinFET epitaxial regions Feb 11, 2021 Issued
Array ( [id] => 18287009 [patent_doc_number] => 20230102481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => LIGHT RECEIVING ELEMENT AND ELECTRONIC EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/906317 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906317
LIGHT RECEIVING ELEMENT AND ELECTRONIC EQUIPMENT Feb 9, 2021 Pending
Array ( [id] => 17708752 [patent_doc_number] => 20220208760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/163544 [patent_app_country] => US [patent_app_date] => 2021-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163544
Semiconductor structure Jan 30, 2021 Issued
Array ( [id] => 18073790 [patent_doc_number] => 11532631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/152003 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 5432 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152003
Semiconductor device and method for fabricating the same Jan 18, 2021 Issued
Array ( [id] => 16812422 [patent_doc_number] => 20210134977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR WITH ONE OR MORE BARRIER REGIONS [patent_app_type] => utility [patent_app_number] => 17/144193 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144193
Semiconductor device including a transistor with one or more barrier regions Jan 7, 2021 Issued
Array ( [id] => 17448344 [patent_doc_number] => 20220068849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SURFACE FINISH STRUCTURE OF MULTI-LAYER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/142271 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142271
SURFACE FINISH STRUCTURE OF MULTI-LAYER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME Jan 5, 2021 Abandoned
Array ( [id] => 16850834 [patent_doc_number] => 20210151579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => NANO MULTILAYER CARBON-RICH LOW-K SPACER [patent_app_type] => utility [patent_app_number] => 17/136169 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136169
Nano multilayer carbon-rich low-k spacer Dec 28, 2020 Issued
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