Search

Thanhha S. Pham

Examiner (ID: 17114, Phone: (571)272-1696 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2812, 2813, 2819, 2894
Total Applications
1792
Issued Applications
1465
Pending Applications
114
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1595750 [patent_doc_number] => 06492270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method for forming copper dual damascene' [patent_app_type] => B1 [patent_app_number] => 09/809832 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4034 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492270.pdf [firstpage_image] =>[orig_patent_app_number] => 09809832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809832
Method for forming copper dual damascene Mar 18, 2001 Issued
Array ( [id] => 5844617 [patent_doc_number] => 20020132471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'High modulus film structure for enhanced electromigration resistance' [patent_app_type] => new [patent_app_number] => 09/810312 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3100 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132471.pdf [firstpage_image] =>[orig_patent_app_number] => 09810312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810312
High modulus film structure for enhanced electromigration resistance Mar 15, 2001 Abandoned
Array ( [id] => 5872653 [patent_doc_number] => 20020048143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Supercapacitor using electrode of new material and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/805921 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2655 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048143.pdf [firstpage_image] =>[orig_patent_app_number] => 09805921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805921
Supercapacitor using electrode of new material and method of manufacturing the same Mar 14, 2001 Issued
Array ( [id] => 6776726 [patent_doc_number] => 20030047806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Component provided with a description' [patent_app_type] => new [patent_app_number] => 10/240872 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2099 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20030047806.pdf [firstpage_image] =>[orig_patent_app_number] => 10240872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/240872
Component with a label Mar 4, 2001 Issued
Array ( [id] => 1328336 [patent_doc_number] => 06603204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics' [patent_app_type] => B2 [patent_app_number] => 09/795431 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4799 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603204.pdf [firstpage_image] =>[orig_patent_app_number] => 09795431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795431
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics Feb 27, 2001 Issued
Array ( [id] => 6358877 [patent_doc_number] => 20020116803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'PACKAGING METHOD FOR ELECTRIC POWER STORAGE UNITS OF AN ULTRACAPACITOR ENERGY STORAGE DEVICE' [patent_app_type] => new [patent_app_number] => 09/790619 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2175 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116803.pdf [firstpage_image] =>[orig_patent_app_number] => 09790619 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790619
Packaging method for electric power storage units of an ultracapacitor energy storage device Feb 22, 2001 Issued
Array ( [id] => 1600206 [patent_doc_number] => 06475831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Methods for a low profile multi-IC chip package connector' [patent_app_type] => B2 [patent_app_number] => 09/792771 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475831.pdf [firstpage_image] =>[orig_patent_app_number] => 09792771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792771
Methods for a low profile multi-IC chip package connector Feb 22, 2001 Issued
Array ( [id] => 1545388 [patent_doc_number] => 06444573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method of making a slot via filled dual damascene structure with a middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/788472 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5154 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444573.pdf [firstpage_image] =>[orig_patent_app_number] => 09788472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788472
Method of making a slot via filled dual damascene structure with a middle stop layer Feb 20, 2001 Issued
Array ( [id] => 6947923 [patent_doc_number] => 20010021557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/785248 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021557.pdf [firstpage_image] =>[orig_patent_app_number] => 09785248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785248
Method of polishing a stack of dielectric layers including a fluorine containing silicon oxide layer Feb 19, 2001 Issued
Array ( [id] => 1195134 [patent_doc_number] => 06726732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Electric energy storage device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/783958 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5526 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/726/06726732.pdf [firstpage_image] =>[orig_patent_app_number] => 09783958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783958
Electric energy storage device and method for manufacturing the same Feb 15, 2001 Issued
Array ( [id] => 1416460 [patent_doc_number] => 06518177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/783561 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 65 [patent_no_of_words] => 16436 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518177.pdf [firstpage_image] =>[orig_patent_app_number] => 09783561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783561
Method of manufacturing a semiconductor device Feb 14, 2001 Issued
Array ( [id] => 1550408 [patent_doc_number] => 06399470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for forming contact holes on conductors having a protective layer using selective etching' [patent_app_type] => B1 [patent_app_number] => 09/781422 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5995 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399470.pdf [firstpage_image] =>[orig_patent_app_number] => 09781422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781422
Method for forming contact holes on conductors having a protective layer using selective etching Feb 12, 2001 Issued
Array ( [id] => 6946244 [patent_doc_number] => 20010020319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => ' METHOD OF MAKING A MULTI-ELECTRODE DOUBLE LAYER CAPACITOR HAVING SINGLE ELECTROLYTE SEAL AND ALUMINUM-IMPREGNATED CARBON CLOTH ELECTRODES\n ' [patent_app_type] => original-publication-amended [patent_app_number] => 09/783728 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23733 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020319.pdf [firstpage_image] =>[orig_patent_app_number] => 09783728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783728
Method of making a multi-electrode double layer capacitor having single electrolyte seal and aluminum-impregnated carbon cloth electrodes Feb 12, 2001 Issued
Array ( [id] => 1410807 [patent_doc_number] => 06534863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Common ball-limiting metallurgy for I/O sites' [patent_app_type] => B2 [patent_app_number] => 09/781121 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3272 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534863.pdf [firstpage_image] =>[orig_patent_app_number] => 09781121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781121
Common ball-limiting metallurgy for I/O sites Feb 8, 2001 Issued
Array ( [id] => 6445118 [patent_doc_number] => 20020149113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Lead-free solder structure and method for high fatigue life' [patent_app_type] => new [patent_app_number] => 09/779812 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5280 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149113.pdf [firstpage_image] =>[orig_patent_app_number] => 09779812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779812
Lead-free solder structure and method for high fatigue life Feb 7, 2001 Issued
Array ( [id] => 1594581 [patent_doc_number] => 06383919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of making a dual damascene structure without middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/778112 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4704 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383919.pdf [firstpage_image] =>[orig_patent_app_number] => 09778112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778112
Method of making a dual damascene structure without middle stop layer Feb 6, 2001 Issued
Array ( [id] => 6276901 [patent_doc_number] => 20020106837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'METHOD OF GENERATING INTEGRATED CIRCUIT FEATURE LAYOUT FOR IMPROVED CHEMICAL MECHANICAL POLISHING' [patent_app_type] => new [patent_app_number] => 09/775761 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106837.pdf [firstpage_image] =>[orig_patent_app_number] => 09775761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775761
Method of generating integrated circuit feature layout for improved chemical mechanical polishing Feb 1, 2001 Issued
Array ( [id] => 1476424 [patent_doc_number] => 06388330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Low dielectric constant etch stop layers in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/776012 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3382 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388330.pdf [firstpage_image] =>[orig_patent_app_number] => 09776012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776012
Low dielectric constant etch stop layers in integrated circuit interconnects Jan 31, 2001 Issued
Array ( [id] => 6885872 [patent_doc_number] => 20010019141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Semiconductor device with capacitive element and method of forming the same' [patent_app_type] => new [patent_app_number] => 09/774041 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10835 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019141.pdf [firstpage_image] =>[orig_patent_app_number] => 09774041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774041
Semiconductor device with capacitive element and method of forming the same Jan 30, 2001 Abandoned
Array ( [id] => 7000651 [patent_doc_number] => 20010053600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Methods for characterizing and reducing adverse effects of texture of semiconductor films' [patent_app_type] => new [patent_app_number] => 09/773312 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12299 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053600.pdf [firstpage_image] =>[orig_patent_app_number] => 09773312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773312
Methods for characterizing and reducing adverse effects of texture of semiconductor films Jan 30, 2001 Abandoned
Menu