Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17188775 [patent_doc_number] => 20210335660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING VOID BETWEEN BONDED WAFERS AND MANUFACTURING METHOD TEHREOF [patent_app_type] => utility [patent_app_number] => 16/857920 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/857920
SEMICONDUCTOR STRUCTURE HAVING VOID BETWEEN BONDED WAFERS AND MANUFACTURING METHOD TEHREOF Apr 23, 2020 Abandoned
Array ( [id] => 17395829 [patent_doc_number] => 11244853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Fully aligned via interconnects with partially removed etch stop layer [patent_app_type] => utility [patent_app_number] => 16/856954 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 13443 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856954
Fully aligned via interconnects with partially removed etch stop layer Apr 22, 2020 Issued
Array ( [id] => 17174085 [patent_doc_number] => 20210327756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => METHOD AND STRUCTURE FOR FORMING FULLY-ALIGNED VIA [patent_app_type] => utility [patent_app_number] => 16/854064 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854064
Method and structure for forming fully-aligned via Apr 20, 2020 Issued
Array ( [id] => 17092939 [patent_doc_number] => 11121137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Semiconductor device with self-aligned landing pad and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/849439 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 8797 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849439
Semiconductor device with self-aligned landing pad and method for fabricating the same Apr 14, 2020 Issued
Array ( [id] => 17787983 [patent_doc_number] => 11411121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/831934 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 15847 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831934
Semiconductor device Mar 26, 2020 Issued
Array ( [id] => 19741333 [patent_doc_number] => 12218181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Barrier layer for metal insulator metal capacitors [patent_app_type] => utility [patent_app_number] => 16/830981 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830981
Barrier layer for metal insulator metal capacitors Mar 25, 2020 Issued
Array ( [id] => 17395830 [patent_doc_number] => 11244854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Dual damascene fully aligned via in interconnects [patent_app_type] => utility [patent_app_number] => 16/828088 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7430 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828088
Dual damascene fully aligned via in interconnects Mar 23, 2020 Issued
Array ( [id] => 17529906 [patent_doc_number] => 11302605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Semiconductor structure comprising via element and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 16/826330 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4158 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826330
Semiconductor structure comprising via element and manufacturing method for the same Mar 22, 2020 Issued
Array ( [id] => 17818511 [patent_doc_number] => 11424133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Metal structure and method of manufacturing the same and metal wire and semiconductor device and electronic device [patent_app_type] => utility [patent_app_number] => 16/825237 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7324 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825237
Metal structure and method of manufacturing the same and metal wire and semiconductor device and electronic device Mar 19, 2020 Issued
Array ( [id] => 19064660 [patent_doc_number] => 11943938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Method for manufacturing a memory device and memory device manufactured through the same method [patent_app_type] => utility [patent_app_number] => 17/252357 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17252357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/252357
Method for manufacturing a memory device and memory device manufactured through the same method Mar 17, 2020 Issued
Array ( [id] => 17590677 [patent_doc_number] => 11328954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Bi metal subtractive etch for trench and via formation [patent_app_type] => utility [patent_app_number] => 16/817988 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3877 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817988
Bi metal subtractive etch for trench and via formation Mar 12, 2020 Issued
Array ( [id] => 17100143 [patent_doc_number] => 20210287934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/817572 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817572
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Mar 11, 2020 Abandoned
Array ( [id] => 17085450 [patent_doc_number] => 20210280457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SELF-ALIGNED BLOCK VIA PATTERNING FOR DUAL DAMASCENE DOUBLE PATTERNED METAL LINES [patent_app_type] => utility [patent_app_number] => 16/811291 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811291
SELF-ALIGNED BLOCK VIA PATTERNING FOR DUAL DAMASCENE DOUBLE PATTERNED METAL LINES Mar 5, 2020 Abandoned
Array ( [id] => 16098403 [patent_doc_number] => 20200203188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => CHIP PACKAGING METHOD AND PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/805850 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805850
Chip packaging method and package structure Mar 1, 2020 Issued
Array ( [id] => 17077900 [patent_doc_number] => 11114315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Chip packaging method and package structure [patent_app_type] => utility [patent_app_number] => 16/805846 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 9821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805846
Chip packaging method and package structure Mar 1, 2020 Issued
Array ( [id] => 16098631 [patent_doc_number] => 20200203302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => CHIP PACKAGING METHOD AND CHIP STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/805853 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805853
Chip packaging method and chip structure Mar 1, 2020 Issued
Array ( [id] => 18263146 [patent_doc_number] => 11610855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Chip packaging method and package structure [patent_app_type] => utility [patent_app_number] => 16/805851 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 8533 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805851
Chip packaging method and package structure Mar 1, 2020 Issued
Array ( [id] => 16715797 [patent_doc_number] => 20210082944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/800163 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800163 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800163
Semiconductor device including a plug connected to a bit line and containing tungsten Feb 24, 2020 Issued
Array ( [id] => 16586095 [patent_doc_number] => 20210020497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/798789 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798789
Semiconductor device and method of fabricating the same Feb 23, 2020 Issued
Array ( [id] => 17040664 [patent_doc_number] => 20210257300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => THIN FILM CONDUCTIVE MATERIAL WITH CONDUCTIVE ETCH STOP LAYER [patent_app_type] => utility [patent_app_number] => 16/792854 [patent_app_country] => US [patent_app_date] => 2020-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/792854
Thin film conductive material with conductive etch stop layer Feb 16, 2020 Issued
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