Thanhha S. Pham

Array ( [id] => 1514549 [patent_doc_number] => 06420260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Ti/Tinx underlayer which enables a highly <111> oriented aluminum interconnect' [patent_app_type] => B1 [patent_app_number] => 09/695941 [patent_app_country] => US [patent_app_date] => 2000-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 8467 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420260.pdf [firstpage_image] =>[orig_patent_app_number] => 09695941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1594657 [patent_doc_number] => 06383935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of reducing dishing and erosion using a sacrificial layer' [patent_app_type] => B1 [patent_app_number] => 09/687162 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1327 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383935.pdf [firstpage_image] =>[orig_patent_app_number] => 09687162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501525 [patent_doc_number] => 06464738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Fabrication method of solid electrolytic capacitor' [patent_app_type] => B1 [patent_app_number] => 09/676532 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4174 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/464/06464738.pdf [firstpage_image] =>[orig_patent_app_number] => 09676532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1476436 [patent_doc_number] => 06388337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Post-processing a completed semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/672672 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388337.pdf [firstpage_image] =>[orig_patent_app_number] => 09672672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416814 [patent_doc_number] => 06509265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Process for manufacturing a contact barrier' [patent_app_type] => B1 [patent_app_number] => 09/666240 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3690 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509265.pdf [firstpage_image] =>[orig_patent_app_number] => 09666240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532526 [patent_doc_number] => 06410406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Semiconductor device including edge bond pads and methods' [patent_app_type] => B1 [patent_app_number] => 09/660782 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3229 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410406.pdf [firstpage_image] =>[orig_patent_app_number] => 09660782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1522951 [patent_doc_number] => 06352564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of making a solid electrolytic capacitor using a conductive polymer film' [patent_app_type] => B1 [patent_app_number] => 09/658495 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 11145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352564.pdf [firstpage_image] =>[orig_patent_app_number] => 09658495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1155849 [patent_doc_number] => 06764939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/658861 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764939.pdf [firstpage_image] =>[orig_patent_app_number] => 09658861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7639760 [patent_doc_number] => 06396156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Flip-chip bonding structure with stress-buffering property and method for making the same' [patent_app_type] => B1 [patent_app_number] => 09/656572 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396156.pdf [firstpage_image] =>[orig_patent_app_number] => 09656572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1448194 [patent_doc_number] => 06454815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Alkaline electrochemical capacitor and electrode fabrication' [patent_app_type] => B1 [patent_app_number] => 09/656197 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2750 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/454/06454815.pdf [firstpage_image] =>[orig_patent_app_number] => 09656197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507174 [patent_doc_number] => 06466428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Ultracapacitor having residual water removed under vacuum' [patent_app_type] => B1 [patent_app_number] => 09/655362 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4990 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466428.pdf [firstpage_image] =>[orig_patent_app_number] => 09655362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1348091 [patent_doc_number] => 06576026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of producing an anode body having a laminate of a plurality of sheets of valve metal foil' [patent_app_type] => B1 [patent_app_number] => 09/654132 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 13119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576026.pdf [firstpage_image] =>[orig_patent_app_number] => 09654132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559952 [patent_doc_number] => 06436850 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of degassing low k dielectric for metal deposition' [patent_app_type] => B1 [patent_app_number] => 09/652132 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436850.pdf [firstpage_image] =>[orig_patent_app_number] => 09652132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1174968 [patent_doc_number] => 06746896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Process and material for low-cost flip-chip solder interconnect structures' [patent_app_type] => B1 [patent_app_number] => 09/648777 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6139 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746896.pdf [firstpage_image] =>[orig_patent_app_number] => 09648777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415709 [patent_doc_number] => 06511912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of forming a non-conformal layer over and exposing a trench' [patent_app_type] => B1 [patent_app_number] => 09/644254 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 4257 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511912.pdf [firstpage_image] =>[orig_patent_app_number] => 09644254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1146709 [patent_doc_number] => 06774041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Polishing method, metallization fabrication method, method for manufacturing semiconductor device and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/637570 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 12405 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774041.pdf [firstpage_image] =>[orig_patent_app_number] => 09637570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324793 [patent_doc_number] => 06329251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Microelectronic fabrication method employing self-aligned selectively deposited silicon layer' [patent_app_type] => 1 [patent_app_number] => 9/636561 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7983 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329251.pdf [firstpage_image] =>[orig_patent_app_number] => 636561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1367866 [patent_doc_number] => 06566263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method of forming an HDP CVD oxide layer over a metal line structure for high aspect ratio design rule' [patent_app_type] => B1 [patent_app_number] => 09/630452 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3333 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566263.pdf [firstpage_image] =>[orig_patent_app_number] => 09630452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1566036 [patent_doc_number] => 06376368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of forming contact structure in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/630292 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7677 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376368.pdf [firstpage_image] =>[orig_patent_app_number] => 09630292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1485331 [patent_doc_number] => 06365497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method for making an I - shaped access transistor having a silicide envelop' [patent_app_type] => B1 [patent_app_number] => 09/629491 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5557 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365497.pdf [firstpage_image] =>[orig_patent_app_number] => 09629491 [rel_patent_id] =>[rel_patent_doc_number] =>)