
Thanhha S. Pham
Examiner (ID: 11625)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2813, 2819, 2812, 2894 |
| Total Applications | 1754 |
| Issued Applications | 1445 |
| Pending Applications | 106 |
| Abandoned Applications | 230 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13667113
[patent_doc_number] => 10163734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Method for manufacturing semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 15/648032
[patent_app_country] => US
[patent_app_date] => 2017-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6887
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648032 | Method for manufacturing semiconductor structure | Jul 11, 2017 | Issued |
Array
(
[id] => 12154677
[patent_doc_number] => 20180025941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'INTERCONNECT STRUCTURE AND FABRICATION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/646225
[patent_app_country] => US
[patent_app_date] => 2017-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5008
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646225
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/646225 | Interconnect structure and fabrication thereof | Jul 10, 2017 | Issued |
Array
(
[id] => 13724367
[patent_doc_number] => 20170373139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => POWER TRENCH MOSFET WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING (UIS) PERFORMANCE AND PREPARATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/646084
[patent_app_country] => US
[patent_app_date] => 2017-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4519
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646084
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/646084 | Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof | Jul 9, 2017 | Issued |
Array
(
[id] => 12129360
[patent_doc_number] => 20180012946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'THIN-FILM TRANSISTOR AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/643206
[patent_app_country] => US
[patent_app_date] => 2017-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13320
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643206
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/643206 | Thin-film transistor and organic light-emitting display device including the same | Jul 5, 2017 | Issued |
Array
(
[id] => 13099055
[patent_doc_number] => 10068873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-04
[patent_title] => Method and apparatus for connecting packages onto printed circuit boards
[patent_app_type] => utility
[patent_app_number] => 15/639987
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15639987
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/639987 | Method and apparatus for connecting packages onto printed circuit boards | Jun 29, 2017 | Issued |
Array
(
[id] => 14705069
[patent_doc_number] => 10380284
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Heterogeneous miniaturization platform
[patent_app_type] => utility
[patent_app_number] => 15/626582
[patent_app_country] => US
[patent_app_date] => 2017-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 10706
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626582
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/626582 | Heterogeneous miniaturization platform | Jun 18, 2017 | Issued |
Array
(
[id] => 12516024
[patent_doc_number] => 10002809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Top contact resistance measurement in vertical FETs
[patent_app_type] => utility
[patent_app_number] => 15/622614
[patent_app_country] => US
[patent_app_date] => 2017-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4829
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622614
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/622614 | Top contact resistance measurement in vertical FETs | Jun 13, 2017 | Issued |
Array
(
[id] => 11967153
[patent_doc_number] => 20170271305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-21
[patent_title] => 'Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages'
[patent_app_type] => utility
[patent_app_number] => 15/615693
[patent_app_country] => US
[patent_app_date] => 2017-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 37354
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615693
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/615693 | Semiconductor device and method of forming embedded wafer level chip scale packages | Jun 5, 2017 | Issued |
Array
(
[id] => 11967325
[patent_doc_number] => 20170271478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-21
[patent_title] => 'TRANSISTOR STRAIN-INDUCING SCHEME'
[patent_app_type] => utility
[patent_app_number] => 15/612137
[patent_app_country] => US
[patent_app_date] => 2017-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5030
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612137
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/612137 | Transistor strain-inducing scheme | Jun 1, 2017 | Issued |
Array
(
[id] => 11945960
[patent_doc_number] => 20170250110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-31
[patent_title] => 'Methods for Isolating Portions of a Loop of Pitch-Multiplied Material and Related Structures'
[patent_app_type] => utility
[patent_app_number] => 15/596288
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 8057
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596288
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596288 | Methods for isolating portions of a loop of pitch-multiplied material and related structures | May 15, 2017 | Issued |
Array
(
[id] => 11867896
[patent_doc_number] => 20170235181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/585225
[patent_app_country] => US
[patent_app_date] => 2017-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 23736
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585225
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/585225 | Active matrix substrate and display device | May 2, 2017 | Issued |
Array
(
[id] => 12498381
[patent_doc_number] => 09997421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-12
[patent_title] => Top contact resistance measurement in vertical FETS
[patent_app_type] => utility
[patent_app_number] => 15/498900
[patent_app_country] => US
[patent_app_date] => 2017-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4829
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498900
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/498900 | Top contact resistance measurement in vertical FETS | Apr 26, 2017 | Issued |
Array
(
[id] => 11854963
[patent_doc_number] => 20170229455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-10
[patent_title] => 'MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS'
[patent_app_type] => utility
[patent_app_number] => 15/494586
[patent_app_country] => US
[patent_app_date] => 2017-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3819
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494586
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/494586 | Minimizing shorting between FinFET epitaxial regions | Apr 23, 2017 | Issued |
Array
(
[id] => 13859255
[patent_doc_number] => 10191345
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 15/484161
[patent_app_country] => US
[patent_app_date] => 2017-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5288
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484161
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/484161 | Display device | Apr 10, 2017 | Issued |
Array
(
[id] => 17092832
[patent_doc_number] => 11121030
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch
[patent_app_type] => utility
[patent_app_number] => 16/473960
[patent_app_country] => US
[patent_app_date] => 2017-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 22
[patent_no_of_words] => 18469
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16473960
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/473960 | Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch | Mar 29, 2017 | Issued |
Array
(
[id] => 12147576
[patent_doc_number] => 09881834
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-30
[patent_title] => 'Contact openings and methods forming same'
[patent_app_type] => utility
[patent_app_number] => 15/462001
[patent_app_country] => US
[patent_app_date] => 2017-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 29
[patent_no_of_words] => 5225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462001
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/462001 | Contact openings and methods forming same | Mar 16, 2017 | Issued |
Array
(
[id] => 13667583
[patent_doc_number] => 10163973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Method for forming the front-side illuminated image sensor device structure with light pipe
[patent_app_type] => utility
[patent_app_number] => 15/461719
[patent_app_country] => US
[patent_app_date] => 2017-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5543
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461719
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/461719 | Method for forming the front-side illuminated image sensor device structure with light pipe | Mar 16, 2017 | Issued |
Array
(
[id] => 13862101
[patent_doc_number] => 10192775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Methods for gapfill in high aspect ratio structures
[patent_app_type] => utility
[patent_app_number] => 15/461847
[patent_app_country] => US
[patent_app_date] => 2017-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 5159
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461847
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/461847 | Methods for gapfill in high aspect ratio structures | Mar 16, 2017 | Issued |
Array
(
[id] => 16773902
[patent_doc_number] => 10985023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-20
[patent_title] => Methods for depositing fluorine/carbon-free conformal tungsten
[patent_app_type] => utility
[patent_app_number] => 15/461842
[patent_app_country] => US
[patent_app_date] => 2017-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 23149
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461842
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/461842 | Methods for depositing fluorine/carbon-free conformal tungsten | Mar 16, 2017 | Issued |
Array
(
[id] => 13121645
[patent_doc_number] => 10079178
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-09-18
[patent_title] => Formation method of semiconductor device structure using multilayer resist layer
[patent_app_type] => utility
[patent_app_number] => 15/461846
[patent_app_country] => US
[patent_app_date] => 2017-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 34
[patent_no_of_words] => 11622
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461846
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/461846 | Formation method of semiconductor device structure using multilayer resist layer | Mar 16, 2017 | Issued |