Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18884941 [patent_doc_number] => 20240008310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Organic Light Emitting Display Device [patent_app_type] => utility [patent_app_number] => 18/213527 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213527
Organic Light Emitting Display Device Jun 22, 2023 Pending
Array ( [id] => 19646474 [patent_doc_number] => 20240420994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => INTERCONNECT LAYER AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/334802 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334802
INTERCONNECT LAYER AND METHOD FOR MANUFACTURING THE SAME Jun 13, 2023 Pending
Array ( [id] => 19634626 [patent_doc_number] => 20240413075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => INTERCONNECT STRUCTURE HAVING HEAT DISSIPATION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/333380 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333380
INTERCONNECT STRUCTURE HAVING HEAT DISSIPATION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME Jun 11, 2023 Pending
Array ( [id] => 19634625 [patent_doc_number] => 20240413074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/207875 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207875
INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME Jun 8, 2023 Pending
Array ( [id] => 19634625 [patent_doc_number] => 20240413074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/207875 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207875
INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME Jun 8, 2023 Pending
Array ( [id] => 19619402 [patent_doc_number] => 20240405082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VIAS and Via Rails for Source/Drain Metal Full Contact [patent_app_type] => utility [patent_app_number] => 18/329166 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329166 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329166
VIAS and Via Rails for Source/Drain Metal Full Contact Jun 4, 2023 Pending
Array ( [id] => 18898590 [patent_doc_number] => 20240014075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => CONTACT FORMATION PROCESS FOR CMOS DEVICES [patent_app_type] => utility [patent_app_number] => 18/206042 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206042
CONTACT FORMATION PROCESS FOR CMOS DEVICES Jun 4, 2023 Pending
Array ( [id] => 18661441 [patent_doc_number] => 20230307455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN [patent_app_type] => utility [patent_app_number] => 18/204231 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204231
REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN May 30, 2023 Pending
Array ( [id] => 19888322 [patent_doc_number] => 12274071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Capacitor integrated with a transistor for logic and memory applications [patent_app_type] => utility [patent_app_number] => 18/326424 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 84 [patent_no_of_words] => 41034 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326424
Capacitor integrated with a transistor for logic and memory applications May 30, 2023 Issued
Array ( [id] => 19604738 [patent_doc_number] => 20240395618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ALL-TUNGSTEN SCHEME FOR SOURCE/DRAIN CONTACT, SOURCE/DRAIN VIA, AND GATE VIA [patent_app_type] => utility [patent_app_number] => 18/324295 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324295
ALL-TUNGSTEN SCHEME FOR SOURCE/DRAIN CONTACT, SOURCE/DRAIN VIA, AND GATE VIA May 25, 2023 Pending
Array ( [id] => 19604738 [patent_doc_number] => 20240395618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ALL-TUNGSTEN SCHEME FOR SOURCE/DRAIN CONTACT, SOURCE/DRAIN VIA, AND GATE VIA [patent_app_type] => utility [patent_app_number] => 18/324295 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324295
ALL-TUNGSTEN SCHEME FOR SOURCE/DRAIN CONTACT, SOURCE/DRAIN VIA, AND GATE VIA May 25, 2023 Pending
Array ( [id] => 20260616 [patent_doc_number] => 12432987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => High dose implantation for ultrathin semiconductor-on-insulator substrates [patent_app_type] => utility [patent_app_number] => 18/323325 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323325
High dose implantation for ultrathin semiconductor-on-insulator substrates May 23, 2023 Issued
Array ( [id] => 18789681 [patent_doc_number] => 20230378394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/200356 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200356
Light emitting device and manufacturing method thereof May 21, 2023 Issued
Array ( [id] => 18866055 [patent_doc_number] => 20230420492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/320432 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320432
SEMICONDUCTOR STRUCTURE May 18, 2023 Pending
Array ( [id] => 18866055 [patent_doc_number] => 20230420492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/320432 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320432
SEMICONDUCTOR STRUCTURE May 18, 2023 Pending
Array ( [id] => 18586110 [patent_doc_number] => 20230268375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD FOR FABRICATING INDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 18/140635 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140635
Method for fabricating inductor module Apr 27, 2023 Issued
Array ( [id] => 18586110 [patent_doc_number] => 20230268375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD FOR FABRICATING INDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 18/140635 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140635
Method for fabricating inductor module Apr 27, 2023 Issued
Array ( [id] => 18586007 [patent_doc_number] => 20230268272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => CHIP STRUCTURE WITH ETCH STOP LAYER [patent_app_type] => utility [patent_app_number] => 18/308875 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308875
Chip structure with etch stop layer Apr 27, 2023 Issued
Array ( [id] => 19796357 [patent_doc_number] => 12237328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Minimizing shorting between FinFET epitaxial regions [patent_app_type] => utility [patent_app_number] => 18/136641 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3910 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18136641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/136641
Minimizing shorting between FinFET epitaxial regions Apr 18, 2023 Issued
Array ( [id] => 19912496 [patent_doc_number] => 12288715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/135622 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 38 [patent_no_of_words] => 3697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135622
Semiconductor device and manufacturing method thereof Apr 16, 2023 Issued
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