Thanhha S. Pham

Array ( [id] => 14301151 [patent_doc_number] => 10290709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces [patent_app_type] => utility [patent_app_number] => 15/504280 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 7417 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15504280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9989497 [patent_doc_number] => 09034700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-19 [patent_title] => 'Integrated circuit devices including finFETs and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 14/491044 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 7689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10208878 [patent_doc_number] => 20150093868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/489965 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6556 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10652322 [patent_doc_number] => 09368588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Integrated circuits with non-volatile memory and methods for manufacture' [patent_app_type] => utility [patent_app_number] => 14/484417 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9354 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10570190 [patent_doc_number] => 09293368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Method for removing electroplated metal facets and reusing a barrier layer without chemical mechanical polishing' [patent_app_type] => utility [patent_app_number] => 14/483894 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2827 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10286058 [patent_doc_number] => 20150171056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/482574 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10178841 [patent_doc_number] => 09209053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Manufacturing method of a conductive shield layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/482378 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6828 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10041999 [patent_doc_number] => 09082712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Device wafer processing method' [patent_app_type] => utility [patent_app_number] => 14/480894 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4062 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9917301 [patent_doc_number] => 20150072506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'WAFER PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/478202 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11417598 [patent_doc_number] => 09564431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Semiconductor structures and methods for multi-level work function' [patent_app_type] => utility [patent_app_number] => 14/469682 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 6858 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14469682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11700239 [patent_doc_number] => 09690149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Active matrix substrate and display device' [patent_app_type] => utility [patent_app_number] => 14/917296 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 23741 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10697087 [patent_doc_number] => 20160043235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FORMATION' [patent_app_type] => utility [patent_app_number] => 14/455992 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10696798 [patent_doc_number] => 20160042945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'COVERAGE OF HIGH ASPECT RATIO FEATURES USING SPIN-ON DIELECTRIC THROUGH A WETTED SURFACE WITHOUT A PRIOR DRYING STEP' [patent_app_type] => utility [patent_app_number] => 14/456235 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10696804 [patent_doc_number] => 20160042952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'Method for Semiconductor Device Fabrication' [patent_app_type] => utility [patent_app_number] => 14/456241 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11740353 [patent_doc_number] => 09704948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof' [patent_app_type] => utility [patent_app_number] => 14/455877 [patent_app_country] => US [patent_app_date] => 2014-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4628 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11214938 [patent_doc_number] => 09443979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Semiconductor devices including trench walls having multiple slopes' [patent_app_type] => utility [patent_app_number] => 14/455036 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 19231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10693522 [patent_doc_number] => 20160039668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'APPARATUS AND METHOD TO FABRICATE MEMS DEVCE' [patent_app_type] => utility [patent_app_number] => 14/454722 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10624617 [patent_doc_number] => 09343567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/454739 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5519 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10255702 [patent_doc_number] => 20150140699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'METHODS OF FORMING OXIDE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/455805 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13640637 [patent_doc_number] => 09847279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Composite lead frame structure [patent_app_type] => utility [patent_app_number] => 14/454807 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6251 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454807 [rel_patent_id] =>[rel_patent_doc_number] =>)