
Thanhha S. Pham
Examiner (ID: 11625)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2813, 2819, 2812, 2894 |
| Total Applications | 1754 |
| Issued Applications | 1445 |
| Pending Applications | 106 |
| Abandoned Applications | 230 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10350983
[patent_doc_number] => 20150235988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-20
[patent_title] => 'INTEGRATED DEVICE COMPRISING STACKED DIES ON REDISTRIBUTION LAYERS'
[patent_app_type] => utility
[patent_app_number] => 14/181371
[patent_app_country] => US
[patent_app_date] => 2014-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10446
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181371
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/181371 | Integrated device comprising stacked dies on redistribution layers | Feb 13, 2014 | Issued |
Array
(
[id] => 10350852
[patent_doc_number] => 20150235857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-20
[patent_title] => 'METHOD OF FORMING SUBSTRATE PATTERN'
[patent_app_type] => utility
[patent_app_number] => 14/180409
[patent_app_country] => US
[patent_app_date] => 2014-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 3839
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14180409
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/180409 | Method of forming substrate pattern | Feb 13, 2014 | Issued |
Array
(
[id] => 9875192
[patent_doc_number] => 08962459
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'Diffusion sources from liquid precursors'
[patent_app_type] => utility
[patent_app_number] => 14/179790
[patent_app_country] => US
[patent_app_date] => 2014-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6916
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179790
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/179790 | Diffusion sources from liquid precursors | Feb 12, 2014 | Issued |
Array
(
[id] => 9656864
[patent_doc_number] => 20140227869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS'
[patent_app_type] => utility
[patent_app_number] => 14/172135
[patent_app_country] => US
[patent_app_date] => 2014-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5591
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172135
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/172135 | Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions | Feb 3, 2014 | Issued |
Array
(
[id] => 14707509
[patent_doc_number] => 10381517
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Aluminum-gallium-indium-phosphorus-based light emitting diode having gallium nitride layer of uneven type and method for manufacturing same
[patent_app_type] => utility
[patent_app_number] => 15/114066
[patent_app_country] => US
[patent_app_date] => 2014-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3256
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114066
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/114066 | Aluminum-gallium-indium-phosphorus-based light emitting diode having gallium nitride layer of uneven type and method for manufacturing same | Jan 28, 2014 | Issued |
Array
(
[id] => 9460447
[patent_doc_number] => 20140124872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER'
[patent_app_type] => utility
[patent_app_number] => 14/152616
[patent_app_country] => US
[patent_app_date] => 2014-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6201
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152616
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/152616 | SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER | Jan 9, 2014 | Abandoned |
Array
(
[id] => 10035576
[patent_doc_number] => 09076903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-07
[patent_title] => 'Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces'
[patent_app_type] => utility
[patent_app_number] => 14/150221
[patent_app_country] => US
[patent_app_date] => 2014-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 13019
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150221
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/150221 | Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces | Jan 7, 2014 | Issued |
Array
(
[id] => 10255754
[patent_doc_number] => 20150140751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'MODIFIED, ETCH-RESISTANT GATE STRUCTURE(S) FACILITATING CIRCUIT FABRICATION'
[patent_app_type] => utility
[patent_app_number] => 14/085906
[patent_app_country] => US
[patent_app_date] => 2013-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085906
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/085906 | Modified, etch-resistant gate structure(s) facilitating circuit fabrication | Nov 20, 2013 | Issued |
Array
(
[id] => 9566020
[patent_doc_number] => 20140183733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'METAL CORE SOLDER BALL AND HEAT DISSIPATION STRUCTURE FOR SEMICONDUCTOR DEVICE USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/082339
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5088
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082339
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/082339 | Metal core solder ball and heat dissipation structure for semiconductor device using the same | Nov 17, 2013 | Issued |
Array
(
[id] => 10563432
[patent_doc_number] => 09287113
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Methods for depositing films on sensitive substrates'
[patent_app_type] => utility
[patent_app_number] => 14/074617
[patent_app_country] => US
[patent_app_date] => 2013-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 16119
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074617
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/074617 | Methods for depositing films on sensitive substrates | Nov 6, 2013 | Issued |
Array
(
[id] => 9909649
[patent_doc_number] => 20150064850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-05
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/074165
[patent_app_country] => US
[patent_app_date] => 2013-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2707
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074165
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/074165 | Method for fabricating semiconductor structure | Nov 6, 2013 | Issued |
Array
(
[id] => 10570219
[patent_doc_number] => 09293398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-22
[patent_title] => 'Land structure for semiconductor package and method therefor'
[patent_app_type] => utility
[patent_app_number] => 14/072845
[patent_app_country] => US
[patent_app_date] => 2013-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 6538
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072845
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/072845 | Land structure for semiconductor package and method therefor | Nov 5, 2013 | Issued |
Array
(
[id] => 10145181
[patent_doc_number] => 09177996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-03
[patent_title] => 'Method for forming ReRAM chips operating at low operating temperatures'
[patent_app_type] => utility
[patent_app_number] => 14/072611
[patent_app_country] => US
[patent_app_date] => 2013-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 9741
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072611
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/072611 | Method for forming ReRAM chips operating at low operating temperatures | Nov 4, 2013 | Issued |
Array
(
[id] => 10060285
[patent_doc_number] => 09099649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-04
[patent_title] => 'Apparatus and method for manufacturing organic light-emitting diode display'
[patent_app_type] => utility
[patent_app_number] => 14/072734
[patent_app_country] => US
[patent_app_date] => 2013-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7538
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072734
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/072734 | Apparatus and method for manufacturing organic light-emitting diode display | Nov 4, 2013 | Issued |
Array
(
[id] => 9463415
[patent_doc_number] => 20140127842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'METHOD FOR FORMING AN OPTICAL MODULATOR'
[patent_app_type] => utility
[patent_app_number] => 14/071820
[patent_app_country] => US
[patent_app_date] => 2013-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 14425
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071820
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/071820 | Method for forming an optical modulator | Nov 4, 2013 | Issued |
Array
(
[id] => 10035375
[patent_doc_number] => 09076699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-07
[patent_title] => 'TSV backside reveal structure and exposing process'
[patent_app_type] => utility
[patent_app_number] => 14/071459
[patent_app_country] => US
[patent_app_date] => 2013-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5567
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071459
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/071459 | TSV backside reveal structure and exposing process | Nov 3, 2013 | Issued |
Array
(
[id] => 9686049
[patent_doc_number] => 20140242815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-28
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/071406
[patent_app_country] => US
[patent_app_date] => 2013-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5245
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071406
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/071406 | Method of manufacturing semiconductor device | Nov 3, 2013 | Issued |
Array
(
[id] => 9978108
[patent_doc_number] => 09024419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-05
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/070676
[patent_app_country] => US
[patent_app_date] => 2013-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 7323
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070676
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/070676 | Method of manufacturing semiconductor device | Nov 3, 2013 | Issued |
Array
(
[id] => 11740231
[patent_doc_number] => 09704824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-11
[patent_title] => 'Semiconductor device and method of forming embedded wafer level chip scale packages'
[patent_app_type] => utility
[patent_app_number] => 14/070509
[patent_app_country] => US
[patent_app_date] => 2013-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 83
[patent_no_of_words] => 37543
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070509
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/070509 | Semiconductor device and method of forming embedded wafer level chip scale packages | Nov 1, 2013 | Issued |
Array
(
[id] => 10583663
[patent_doc_number] => 09305788
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/066436
[patent_app_country] => US
[patent_app_date] => 2013-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 5031
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14066436
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/066436 | Method of fabricating semiconductor device | Oct 28, 2013 | Issued |