Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8469714 [patent_doc_number] => 08298892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Fabricating method of insulator' [patent_app_type] => utility [patent_app_number] => 13/241295 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1744 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241295
Fabricating method of insulator Sep 22, 2011 Issued
Array ( [id] => 9496437 [patent_doc_number] => 08735250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Methods of forming gates of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/241957 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 7292 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241957 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241957
Methods of forming gates of semiconductor devices Sep 22, 2011 Issued
Array ( [id] => 9311690 [patent_doc_number] => 08652908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/240327 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6172 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240327 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240327
Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same Sep 21, 2011 Issued
Array ( [id] => 8227971 [patent_doc_number] => 20120142176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Methods of Forming Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/239858 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239858
Methods of forming semiconductor devices Sep 21, 2011 Issued
Array ( [id] => 9844111 [patent_doc_number] => 08946026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Methods of fabricating a semiconductor device including metal gate electrodes' [patent_app_type] => utility [patent_app_number] => 13/238284 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9309 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238284
Methods of fabricating a semiconductor device including metal gate electrodes Sep 20, 2011 Issued
Array ( [id] => 8642526 [patent_doc_number] => 08367509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Self-aligned method for forming contact of device with reduced step height' [patent_app_type] => utility [patent_app_number] => 13/239030 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 3382 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239030
Self-aligned method for forming contact of device with reduced step height Sep 20, 2011 Issued
Array ( [id] => 10888072 [patent_doc_number] => 08912067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Method for manufacturing MOS transistors with different types of gate stacks' [patent_app_type] => utility [patent_app_number] => 13/237738 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1994 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237738
Method for manufacturing MOS transistors with different types of gate stacks Sep 19, 2011 Issued
Array ( [id] => 8042373 [patent_doc_number] => 20120070920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'Method for mounting luminescent device' [patent_app_type] => utility [patent_app_number] => 13/137855 [patent_app_country] => US [patent_app_date] => 2011-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3556 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20120070920.pdf [firstpage_image] =>[orig_patent_app_number] => 13137855 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137855
Method for mounting luminescent device Sep 18, 2011 Issued
Array ( [id] => 8042485 [patent_doc_number] => 20120070976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/234558 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20120070976.pdf [firstpage_image] =>[orig_patent_app_number] => 13234558 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234558
Methods of manufacturing semiconductor devices Sep 15, 2011 Issued
Array ( [id] => 8430326 [patent_doc_number] => 20120252201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/234410 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234410
Method for fabricating semiconductor device Sep 15, 2011 Issued
Array ( [id] => 7711221 [patent_doc_number] => 20120003798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN' [patent_app_type] => utility [patent_app_number] => 13/233297 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3859 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13233297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/233297
REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN Sep 14, 2011 Abandoned
Array ( [id] => 8090327 [patent_doc_number] => 20120080767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Solid-state imaging device, method for manufacturing the same, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/137775 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12932 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20120080767.pdf [firstpage_image] =>[orig_patent_app_number] => 13137775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137775
Solid-state imaging device, method for manufacturing the same, and electronic apparatus Sep 11, 2011 Issued
Array ( [id] => 8621837 [patent_doc_number] => 08354752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/215857 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 43 [patent_no_of_words] => 7669 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13215857 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215857
Semiconductor devices Aug 22, 2011 Issued
Array ( [id] => 7656887 [patent_doc_number] => 20110306156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'SURFACE GRATINGS ON VCSELS FOR POLARIZATION PINNING' [patent_app_type] => utility [patent_app_number] => 13/210306 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3612 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20110306156.pdf [firstpage_image] =>[orig_patent_app_number] => 13210306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210306
Surface gratings on VCSELS for polarization pinning Aug 14, 2011 Issued
Array ( [id] => 8571650 [patent_doc_number] => 08338295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method of fabricating metal interconnection and method of fabricating image sensor using the same' [patent_app_type] => utility [patent_app_number] => 13/206703 [patent_app_country] => US [patent_app_date] => 2011-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 6067 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13206703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/206703
Method of fabricating metal interconnection and method of fabricating image sensor using the same Aug 9, 2011 Issued
Array ( [id] => 8586276 [patent_doc_number] => 20130005097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METHOD FOR INTEGRATING REPLACEMENT GATE IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/379169 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4300 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13379169 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/379169
Method for integrating replacement gate in semiconductor device Aug 1, 2011 Issued
Array ( [id] => 8989944 [patent_doc_number] => 20130217225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/819431 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6038 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13819431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/819431
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Jul 28, 2011 Abandoned
Array ( [id] => 8277990 [patent_doc_number] => 20120171855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/190012 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13190012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190012
Methods to adjust threshold voltage in semiconductor devices Jul 24, 2011 Issued
Array ( [id] => 7558991 [patent_doc_number] => 20110272822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors' [patent_app_type] => utility [patent_app_number] => 13/187730 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3459 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20110272822.pdf [firstpage_image] =>[orig_patent_app_number] => 13187730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187730
Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors Jul 20, 2011 Abandoned
Array ( [id] => 8780140 [patent_doc_number] => 20130102115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/806964 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13830 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13806964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/806964
METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE Jun 30, 2011 Abandoned
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