Thanhha S. Pham

Array ( [id] => 7500766 [patent_doc_number] => 20110263124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/067840 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5050 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263124.pdf [firstpage_image] =>[orig_patent_app_number] => 13067840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7700777 [patent_doc_number] => 20110225813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS' [patent_app_type] => utility [patent_app_number] => 13/152918 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5026 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225813.pdf [firstpage_image] =>[orig_patent_app_number] => 13152918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8591837 [patent_doc_number] => 08349713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'High speed laser crystallization of particles of photovoltaic solar cells' [patent_app_type] => utility [patent_app_number] => 13/113386 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3173 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113386 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7662868 [patent_doc_number] => 20110312137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'Vertical Power MOSFET and IGBT Fabrication Process with Two Fewer Photomasks' [patent_app_type] => utility [patent_app_number] => 13/113797 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3965 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20110312137.pdf [firstpage_image] =>[orig_patent_app_number] => 13113797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8502644 [patent_doc_number] => 20120302052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Methods of Forming Electrical Contacts' [patent_app_type] => utility [patent_app_number] => 13/113281 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 7438 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6042425 [patent_doc_number] => 20110204502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'Method of Manufacturing A Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/101199 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7325 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204502.pdf [firstpage_image] =>[orig_patent_app_number] => 13101199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8759957 [patent_doc_number] => 08420477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method for fabricating a gate dielectric layer and for fabricating a gate structure' [patent_app_type] => utility [patent_app_number] => 13/095291 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2268 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8549179 [patent_doc_number] => 08324059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method of fabricating a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 13/092990 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6165993 [patent_doc_number] => 20110195568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/088954 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 4284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195568.pdf [firstpage_image] =>[orig_patent_app_number] => 13088954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111744 [patent_doc_number] => 20110189840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES' [patent_app_type] => utility [patent_app_number] => 13/087646 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6062 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20110189840.pdf [firstpage_image] =>[orig_patent_app_number] => 13087646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6106178 [patent_doc_number] => 20110187000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'Integrated Circuits Having TSVS Including Metal Gettering Dielectric Liners' [patent_app_type] => utility [patent_app_number] => 13/083992 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4328 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20110187000.pdf [firstpage_image] =>[orig_patent_app_number] => 13083992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8125661 [patent_doc_number] => 20120087378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'Method and Apparatus for Producing Gallium Arsenide and Silicon Composites and Devices Incorporating Same' [patent_app_type] => utility [patent_app_number] => 13/084052 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9423 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20120087378.pdf [firstpage_image] =>[orig_patent_app_number] => 13084052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8439697 [patent_doc_number] => 20120256313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS' [patent_app_type] => utility [patent_app_number] => 13/080105 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8772308 [patent_doc_number] => 08426263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET)' [patent_app_type] => utility [patent_app_number] => 13/077569 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6176321 [patent_doc_number] => 20110177662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'Method of Forming Trench-Gate Field Effect Transistors' [patent_app_type] => utility [patent_app_number] => 13/075091 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20110177662.pdf [firstpage_image] =>[orig_patent_app_number] => 13075091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6189092 [patent_doc_number] => 20110171797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/069273 [patent_app_country] => US [patent_app_date] => 2011-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4420 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171797.pdf [firstpage_image] =>[orig_patent_app_number] => 13069273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8538744 [patent_doc_number] => 08314465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Dielectric layer for semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/039811 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4720 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8897161 [patent_doc_number] => 08476685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Image sensor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/023754 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2107 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6137321 [patent_doc_number] => 20110127573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'BI-DIRECTIONAL TRANSISTOR WITH BY-PASS PATH AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/023255 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20110127573.pdf [firstpage_image] =>[orig_patent_app_number] => 13023255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4526765 [patent_doc_number] => 07952148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Method of manufacturing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/929333 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10456 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952148.pdf [firstpage_image] =>[orig_patent_app_number] => 12929333 [rel_patent_id] =>[rel_patent_doc_number] =>)