
Thanhha S. Pham
Examiner (ID: 11625)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2813, 2819, 2812, 2894 |
| Total Applications | 1754 |
| Issued Applications | 1445 |
| Pending Applications | 106 |
| Abandoned Applications | 230 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9130348
[patent_doc_number] => 08578305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure'
[patent_app_type] => utility
[patent_app_number] => 12/984927
[patent_app_country] => US
[patent_app_date] => 2011-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3971
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984927
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/984927 | Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure | Jan 4, 2011 | Issued |
Array
(
[id] => 6119769
[patent_doc_number] => 20110076856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'SEMICONDUCTOR DIE WITH PROTECTIVE LAYER AND RELATED METHOD OF PROCESSING A SEMICONDUCTOR WAFER'
[patent_app_type] => utility
[patent_app_number] => 12/961795
[patent_app_country] => US
[patent_app_date] => 2010-12-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0076/20110076856.pdf
[firstpage_image] =>[orig_patent_app_number] => 12961795
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/961795 | Semiconductor die with protective layer and related method of processing a semiconductor wafer | Dec 6, 2010 | Issued |
Array
(
[id] => 8340691
[patent_doc_number] => 08242611
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[patent_kind] => B2
[patent_issue_date] => 2012-08-14
[patent_title] => 'Bonding metallurgy for three-dimensional interconnect'
[patent_app_type] => utility
[patent_app_number] => 12/944377
[patent_app_country] => US
[patent_app_date] => 2010-11-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/944377 | Bonding metallurgy for three-dimensional interconnect | Nov 10, 2010 | Issued |
Array
(
[id] => 7988973
[patent_doc_number] => 08076784
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-13
[patent_title] => 'Stacked semiconductor chips'
[patent_app_type] => utility
[patent_app_number] => 12/904561
[patent_app_country] => US
[patent_app_date] => 2010-10-14
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12904561
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/904561 | Stacked semiconductor chips | Oct 13, 2010 | Issued |
Array
(
[id] => 8196387
[patent_doc_number] => RE043412
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2012-05-29
[patent_title] => 'LED with self aligned bond pad'
[patent_app_type] => reissue
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[patent_app_country] => US
[patent_app_date] => 2010-10-06
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[pdf_file] => patents/RE/043/RE043412.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/899228 | LED with self aligned bond pad | Oct 5, 2010 | Issued |
Array
(
[id] => 5993120
[patent_doc_number] => 20110014773
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[patent_kind] => A1
[patent_issue_date] => 2011-01-20
[patent_title] => 'METHOD FOR FABRICATING A METAL GATE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/890725
[patent_app_country] => US
[patent_app_date] => 2010-09-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/890725 | Method for fabricating a metal gate structure | Sep 26, 2010 | Issued |
Array
(
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[patent_issue_date] => 2011-01-20
[patent_title] => 'METHOD FOR FABRICATING A METAL GATE STRUCTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/889410 | METHOD FOR FABRICATING A METAL GATE STRUCTURE | Sep 23, 2010 | Abandoned |
Array
(
[id] => 5976986
[patent_doc_number] => 20110070713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-24
[patent_title] => 'METHOD OF MANUFACTURING ELECTRONIC COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 12/882649
[patent_app_country] => US
[patent_app_date] => 2010-09-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/882649 | Method of manufacturing electronic component | Sep 14, 2010 | Issued |
Array
(
[id] => 8968575
[patent_doc_number] => 08507386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-13
[patent_title] => 'Lateral uniformity in silicon recess etch'
[patent_app_type] => utility
[patent_app_number] => 12/880959
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[patent_app_date] => 2010-09-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/880959 | Lateral uniformity in silicon recess etch | Sep 12, 2010 | Issued |
Array
(
[id] => 7818074
[patent_doc_number] => 20120064694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL'
[patent_app_type] => utility
[patent_app_number] => 12/880419
[patent_app_country] => US
[patent_app_date] => 2010-09-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/880419 | Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal | Sep 12, 2010 | Issued |
Array
(
[id] => 8772354
[patent_doc_number] => 08426309
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[patent_issue_date] => 2013-04-23
[patent_title] => 'Graphene nanoelectric device fabrication'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/879400 | Graphene nanoelectric device fabrication | Sep 9, 2010 | Issued |
Array
(
[id] => 8214050
[patent_doc_number] => 08193056
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Array
(
[id] => 6202472
[patent_doc_number] => 20110065258
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[patent_title] => 'METHOD OF PRODUCING BONDED SUBSTRATE'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/876510 | Method for forming an interconnect structure | Sep 6, 2010 | Issued |
Array
(
[id] => 6007567
[patent_doc_number] => 20110059598
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[patent_title] => 'METHOD FOR STABILIZING GERMANIUM NANOWIRES OBTAINED BY CONDENSATION'
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/862829 | Method for manufacturing semiconductor device | Aug 24, 2010 | Issued |