Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9130348 [patent_doc_number] => 08578305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure' [patent_app_type] => utility [patent_app_number] => 12/984927 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984927 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984927
Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure Jan 4, 2011 Issued
Array ( [id] => 6119769 [patent_doc_number] => 20110076856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'SEMICONDUCTOR DIE WITH PROTECTIVE LAYER AND RELATED METHOD OF PROCESSING A SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 12/961795 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6944 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076856.pdf [firstpage_image] =>[orig_patent_app_number] => 12961795 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961795
Semiconductor die with protective layer and related method of processing a semiconductor wafer Dec 6, 2010 Issued
Array ( [id] => 8340691 [patent_doc_number] => 08242611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Bonding metallurgy for three-dimensional interconnect' [patent_app_type] => utility [patent_app_number] => 12/944377 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12944377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944377
Bonding metallurgy for three-dimensional interconnect Nov 10, 2010 Issued
Array ( [id] => 7988973 [patent_doc_number] => 08076784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Stacked semiconductor chips' [patent_app_type] => utility [patent_app_number] => 12/904561 [patent_app_country] => US [patent_app_date] => 2010-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4862 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076784.pdf [firstpage_image] =>[orig_patent_app_number] => 12904561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/904561
Stacked semiconductor chips Oct 13, 2010 Issued
Array ( [id] => 8196387 [patent_doc_number] => RE043412 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-05-29 [patent_title] => 'LED with self aligned bond pad' [patent_app_type] => reissue [patent_app_number] => 12/899228 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2146 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/043/RE043412.pdf [firstpage_image] =>[orig_patent_app_number] => 12899228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899228
LED with self aligned bond pad Oct 5, 2010 Issued
Array ( [id] => 5993120 [patent_doc_number] => 20110014773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD FOR FABRICATING A METAL GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/890725 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4383 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20110014773.pdf [firstpage_image] =>[orig_patent_app_number] => 12890725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890725
Method for fabricating a metal gate structure Sep 26, 2010 Issued
Array ( [id] => 5989256 [patent_doc_number] => 20110012205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD FOR FABRICATING A METAL GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/889410 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4403 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012205.pdf [firstpage_image] =>[orig_patent_app_number] => 12889410 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889410
METHOD FOR FABRICATING A METAL GATE STRUCTURE Sep 23, 2010 Abandoned
Array ( [id] => 5976986 [patent_doc_number] => 20110070713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'METHOD OF MANUFACTURING ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 12/882649 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9700 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20110070713.pdf [firstpage_image] =>[orig_patent_app_number] => 12882649 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/882649
Method of manufacturing electronic component Sep 14, 2010 Issued
Array ( [id] => 8968575 [patent_doc_number] => 08507386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Lateral uniformity in silicon recess etch' [patent_app_type] => utility [patent_app_number] => 12/880959 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12880959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880959
Lateral uniformity in silicon recess etch Sep 12, 2010 Issued
Array ( [id] => 7818074 [patent_doc_number] => 20120064694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL' [patent_app_type] => utility [patent_app_number] => 12/880419 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064694.pdf [firstpage_image] =>[orig_patent_app_number] => 12880419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880419
Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal Sep 12, 2010 Issued
Array ( [id] => 8772354 [patent_doc_number] => 08426309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Graphene nanoelectric device fabrication' [patent_app_type] => utility [patent_app_number] => 12/879400 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5570 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12879400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879400
Graphene nanoelectric device fabrication Sep 9, 2010 Issued
Array ( [id] => 8214050 [patent_doc_number] => 08193056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/878320 [patent_app_country] => US [patent_app_date] => 2010-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4081 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193056.pdf [firstpage_image] =>[orig_patent_app_number] => 12878320 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/878320
Method of manufacturing semiconductor device Sep 8, 2010 Issued
Array ( [id] => 6202472 [patent_doc_number] => 20110065258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'METHOD OF PRODUCING BONDED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/877439 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5855 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065258.pdf [firstpage_image] =>[orig_patent_app_number] => 12877439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877439
METHOD OF PRODUCING BONDED SUBSTRATE Sep 7, 2010 Abandoned
Array ( [id] => 7807686 [patent_doc_number] => 20120058640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'METHOD FOR FORMING AN INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/876510 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3736 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20120058640.pdf [firstpage_image] =>[orig_patent_app_number] => 12876510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876510
Method for forming an interconnect structure Sep 6, 2010 Issued
Array ( [id] => 6007567 [patent_doc_number] => 20110059598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'METHOD FOR STABILIZING GERMANIUM NANOWIRES OBTAINED BY CONDENSATION' [patent_app_type] => utility [patent_app_number] => 12/875729 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3794 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20110059598.pdf [firstpage_image] =>[orig_patent_app_number] => 12875729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875729
Method for stabilizing germanium nanowires obtained by condensation Sep 2, 2010 Issued
Array ( [id] => 7755904 [patent_doc_number] => 20120028459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'MANUFACTURING PROCESS OF CIRCUIT SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/873540 [patent_app_country] => US [patent_app_date] => 2010-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3985 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20120028459.pdf [firstpage_image] =>[orig_patent_app_number] => 12873540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873540
MANUFACTURING PROCESS OF CIRCUIT SUBSTRATE Aug 31, 2010 Abandoned
Array ( [id] => 9350278 [patent_doc_number] => 08669169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Diffusion sources from liquid precursors' [patent_app_type] => utility [patent_app_number] => 12/873320 [patent_app_country] => US [patent_app_date] => 2010-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12873320 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873320
Diffusion sources from liquid precursors Aug 31, 2010 Issued
Array ( [id] => 9086223 [patent_doc_number] => 08557650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Patterning a gate stack of a non-volatile memory (NVM) using a dummy gate stack' [patent_app_type] => utility [patent_app_number] => 12/872070 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 6561 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12872070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872070
Patterning a gate stack of a non-volatile memory (NVM) using a dummy gate stack Aug 30, 2010 Issued
Array ( [id] => 7791088 [patent_doc_number] => 20120052644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'METHOD FOR FABRICATING MOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/868739 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20120052644.pdf [firstpage_image] =>[orig_patent_app_number] => 12868739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868739
Method for fabricating MOS transistor Aug 25, 2010 Issued
Array ( [id] => 8797002 [patent_doc_number] => 08435869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/862829 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3128 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12862829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862829
Method for manufacturing semiconductor device Aug 24, 2010 Issued
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