Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4433608 [patent_doc_number] => 07969020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Die stacking apparatus and method' [patent_app_type] => utility [patent_app_number] => 12/868339 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3828 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969020.pdf [firstpage_image] =>[orig_patent_app_number] => 12868339 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868339
Die stacking apparatus and method Aug 24, 2010 Issued
Array ( [id] => 6368712 [patent_doc_number] => 20100314680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/862020 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3679 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314680.pdf [firstpage_image] =>[orig_patent_app_number] => 12862020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862020
Memory array Aug 23, 2010 Issued
Array ( [id] => 7784324 [patent_doc_number] => 20120045880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/860939 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2204 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045880.pdf [firstpage_image] =>[orig_patent_app_number] => 12860939 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860939
Metal gate transistor and method for fabricating the same Aug 22, 2010 Issued
Array ( [id] => 8621435 [patent_doc_number] => 08354348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 12/859490 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 79 [patent_no_of_words] => 22692 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12859490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859490
Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate Aug 18, 2010 Issued
Array ( [id] => 5971050 [patent_doc_number] => 20110151600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHOD OF MANUFACTURING DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/856819 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4846 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20110151600.pdf [firstpage_image] =>[orig_patent_app_number] => 12856819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856819
Method of manufacturing display device Aug 15, 2010 Issued
Array ( [id] => 8955845 [patent_doc_number] => 08501617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication' [patent_app_type] => utility [patent_app_number] => 12/855870 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7803 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12855870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855870
Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication Aug 12, 2010 Issued
Array ( [id] => 7737440 [patent_doc_number] => 20120017970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'Method and System of Layered Thin-Film Device With Ceramic Substrates' [patent_app_type] => utility [patent_app_number] => 12/854190 [patent_app_country] => US [patent_app_date] => 2010-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20120017970.pdf [firstpage_image] =>[orig_patent_app_number] => 12854190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/854190
Method and System of Layered Thin-Film Device With Ceramic Substrates Aug 10, 2010 Abandoned
Array ( [id] => 6256336 [patent_doc_number] => 20100295176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 12/852826 [patent_app_country] => US [patent_app_date] => 2010-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4935 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295176.pdf [firstpage_image] =>[orig_patent_app_number] => 12852826 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/852826
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT Aug 8, 2010 Abandoned
Array ( [id] => 6055179 [patent_doc_number] => 20110111539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/846839 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4241 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20110111539.pdf [firstpage_image] =>[orig_patent_app_number] => 12846839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/846839
METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE Jul 29, 2010 Abandoned
Array ( [id] => 8690505 [patent_doc_number] => 08390034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Methods for isolating portions of a loop of pitch-multiplied material and related structures' [patent_app_type] => utility [patent_app_number] => 12/845167 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 8082 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12845167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/845167
Methods for isolating portions of a loop of pitch-multiplied material and related structures Jul 27, 2010 Issued
Array ( [id] => 6196194 [patent_doc_number] => 20110027952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY DEPOSITING A HARD MASK FOR THE SELECTIVE EPITAXIAL GROWTH' [patent_app_type] => utility [patent_app_number] => 12/842439 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9044 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20110027952.pdf [firstpage_image] =>[orig_patent_app_number] => 12842439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842439
Formation of a channel semiconductor alloy by depositing a hard mask for the selective epitaxial growth Jul 22, 2010 Issued
Array ( [id] => 6441266 [patent_doc_number] => 20100279499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'METHOD FOR MANUFACTURING A MEMORY' [patent_app_type] => utility [patent_app_number] => 12/839387 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2490 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20100279499.pdf [firstpage_image] =>[orig_patent_app_number] => 12839387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/839387
Method for manufacturing a memory Jul 18, 2010 Issued
Array ( [id] => 5953321 [patent_doc_number] => 20110034023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/834700 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3886 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20110034023.pdf [firstpage_image] =>[orig_patent_app_number] => 12834700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834700
SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION Jul 11, 2010 Abandoned
Array ( [id] => 6096631 [patent_doc_number] => 20110003468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES' [patent_app_type] => utility [patent_app_number] => 12/824900 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20110003468.pdf [firstpage_image] =>[orig_patent_app_number] => 12824900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824900
Method for fabricating semiconductor device with buried gates Jun 27, 2010 Issued
Array ( [id] => 8351952 [patent_doc_number] => 08247281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers' [patent_app_type] => utility [patent_app_number] => 12/822789 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8197 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822789
Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers Jun 23, 2010 Issued
Array ( [id] => 6397448 [patent_doc_number] => 20100304563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS' [patent_app_type] => utility [patent_app_number] => 12/814942 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5157 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20100304563.pdf [firstpage_image] =>[orig_patent_app_number] => 12814942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/814942
MOSFET structure with multiple self-aligned silicide contacts Jun 13, 2010 Issued
Array ( [id] => 9703705 [patent_doc_number] => 08828765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces' [patent_app_type] => utility [patent_app_number] => 12/797590 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12992 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797590
Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces Jun 8, 2010 Issued
Array ( [id] => 7580403 [patent_doc_number] => 20110294286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'REVERSE PLANARIZATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/789709 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20110294286.pdf [firstpage_image] =>[orig_patent_app_number] => 12789709 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789709
Reverse planarization method May 27, 2010 Issued
Array ( [id] => 8625098 [patent_doc_number] => 08357592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Method and apparatus for manufacturing semiconductor substrate dedicated to semiconductor device, and method and apparatus for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/787750 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 15543 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787750
Method and apparatus for manufacturing semiconductor substrate dedicated to semiconductor device, and method and apparatus for manufacturing semiconductor device May 25, 2010 Issued
Array ( [id] => 6641064 [patent_doc_number] => 20100227463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Methods of Forming Pad Structures and Related Methods of Manufacturing Recessed Channel Transistors that Include Such Pad Structures' [patent_app_type] => utility [patent_app_number] => 12/785544 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20100227463.pdf [firstpage_image] =>[orig_patent_app_number] => 12785544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785544
Recessed channel transistors that include pad structures May 23, 2010 Issued
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