Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 34474 [patent_doc_number] => 07786468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Layer transfer of low defect SiGe using an etch-back process' [patent_app_type] => utility [patent_app_number] => 12/181613 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 3966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/786/07786468.pdf [firstpage_image] =>[orig_patent_app_number] => 12181613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181613
Layer transfer of low defect SiGe using an etch-back process Jul 28, 2008 Issued
Array ( [id] => 9020270 [patent_doc_number] => 08530255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Method of manufacturing semiconductor laser, semiconductor laser, optical pickup, optical disk device, method of manufacturing semiconductor device, semiconductor device, and method of growing nitride type group III-V compound semiconductor layer' [patent_app_type] => utility [patent_app_number] => 12/180915 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 74 [patent_no_of_words] => 18661 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12180915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180915
Method of manufacturing semiconductor laser, semiconductor laser, optical pickup, optical disk device, method of manufacturing semiconductor device, semiconductor device, and method of growing nitride type group III-V compound semiconductor layer Jul 27, 2008 Issued
Array ( [id] => 4583055 [patent_doc_number] => 07851346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Bonding metallurgy for three-dimensional interconnect' [patent_app_type] => utility [patent_app_number] => 12/176770 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3032 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851346.pdf [firstpage_image] =>[orig_patent_app_number] => 12176770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176770
Bonding metallurgy for three-dimensional interconnect Jul 20, 2008 Issued
Array ( [id] => 4958036 [patent_doc_number] => 20080272460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'THIN FILM RESISTORS INTEGRATED AT TWO DIFFERENT METAL INTERCONNECT LEVELS OF SINGLE DIE' [patent_app_type] => utility [patent_app_number] => 12/176612 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3705 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272460.pdf [firstpage_image] =>[orig_patent_app_number] => 12176612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176612
Thin film resistors integrated at two different metal single die Jul 20, 2008 Issued
Array ( [id] => 4775921 [patent_doc_number] => 20080283919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION' [patent_app_type] => utility [patent_app_number] => 12/169190 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6214 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283919.pdf [firstpage_image] =>[orig_patent_app_number] => 12169190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169190
Single and double-gate pseudo-FET devices for semiconductor materials evaluation Jul 7, 2008 Issued
Array ( [id] => 5464706 [patent_doc_number] => 20090324906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SEMICONDUCTOR WITH TOP-SIDE WRAP-AROUND FLANGE CONTACT' [patent_app_type] => utility [patent_app_number] => 12/147370 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2695 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0324/20090324906.pdf [firstpage_image] =>[orig_patent_app_number] => 12147370 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147370
SEMICONDUCTOR WITH TOP-SIDE WRAP-AROUND FLANGE CONTACT Jun 25, 2008 Abandoned
Array ( [id] => 5464810 [patent_doc_number] => 20090325010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'ADAPTIVE COMPRESSOR SURGE CONTROL IN A FUEL CELL SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/145597 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20090325010.pdf [firstpage_image] =>[orig_patent_app_number] => 12145597 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145597
Adaptive compressor surge control in a fuel cell system Jun 24, 2008 Issued
Array ( [id] => 63801 [patent_doc_number] => 07759243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method for forming an on-chip high frequency electro-static discharge device' [patent_app_type] => utility [patent_app_number] => 12/144089 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 3180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759243.pdf [firstpage_image] =>[orig_patent_app_number] => 12144089 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144089
Method for forming an on-chip high frequency electro-static discharge device Jun 22, 2008 Issued
Array ( [id] => 9440745 [patent_doc_number] => 08709855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Intralevel conductive light shield' [patent_app_type] => utility [patent_app_number] => 12/133379 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15440 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12133379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133379
Intralevel conductive light shield Jun 4, 2008 Issued
Array ( [id] => 4859750 [patent_doc_number] => 20080268600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS' [patent_app_type] => utility [patent_app_number] => 12/131973 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5127 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20080268600.pdf [firstpage_image] =>[orig_patent_app_number] => 12131973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131973
MOSFET structure with multiple self-aligned silicide contacts Jun 2, 2008 Issued
Array ( [id] => 112372 [patent_doc_number] => 07713837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Low temperature fusion bonding with high surface energy using a wet chemical treatment' [patent_app_type] => utility [patent_app_number] => 12/128259 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3513 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713837.pdf [firstpage_image] =>[orig_patent_app_number] => 12128259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128259
Low temperature fusion bonding with high surface energy using a wet chemical treatment May 27, 2008 Issued
Array ( [id] => 4432578 [patent_doc_number] => 07897448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-01 [patent_title] => 'Formation of high voltage transistor with high breakdown voltage' [patent_app_type] => utility [patent_app_number] => 12/122489 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3572 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/897/07897448.pdf [firstpage_image] =>[orig_patent_app_number] => 12122489 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122489
Formation of high voltage transistor with high breakdown voltage May 15, 2008 Issued
Array ( [id] => 4778934 [patent_doc_number] => 20080286932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/152800 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1824 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20080286932.pdf [firstpage_image] =>[orig_patent_app_number] => 12152800 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/152800
Method of manufacturing semiconductor device May 14, 2008 Abandoned
Array ( [id] => 5458330 [patent_doc_number] => 20090258482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'METHOD FOR FABRICATING A METAL GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/101160 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20090258482.pdf [firstpage_image] =>[orig_patent_app_number] => 12101160 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101160
Method for fabricating a metal gate structure Apr 10, 2008 Issued
Array ( [id] => 4483671 [patent_doc_number] => 07902019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Dielectric layer for semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/098373 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4690 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902019.pdf [firstpage_image] =>[orig_patent_app_number] => 12098373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/098373
Dielectric layer for semiconductor device and method of manufacturing the same Apr 3, 2008 Issued
Array ( [id] => 4778919 [patent_doc_number] => 20080286917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS' [patent_app_type] => utility [patent_app_number] => 12/062749 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9400 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20080286917.pdf [firstpage_image] =>[orig_patent_app_number] => 12062749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062749
Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics Apr 3, 2008 Issued
Array ( [id] => 4813429 [patent_doc_number] => 20080194060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/078587 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18764 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194060.pdf [firstpage_image] =>[orig_patent_app_number] => 12078587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078587
Semiconductor device and method of manufacturing the same Apr 1, 2008 Issued
Array ( [id] => 4455803 [patent_doc_number] => 07892932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure' [patent_app_type] => utility [patent_app_number] => 12/054699 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3934 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/892/07892932.pdf [firstpage_image] =>[orig_patent_app_number] => 12054699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054699
Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure Mar 24, 2008 Issued
Array ( [id] => 4719513 [patent_doc_number] => 20080242036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/053689 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7298 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242036.pdf [firstpage_image] =>[orig_patent_app_number] => 12053689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053689
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Mar 23, 2008 Abandoned
Array ( [id] => 4727362 [patent_doc_number] => 20080206906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/076848 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206906.pdf [firstpage_image] =>[orig_patent_app_number] => 12076848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076848
Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device Mar 23, 2008 Abandoned
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