Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4958020 [patent_doc_number] => 20080272444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/050719 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4442 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272444.pdf [firstpage_image] =>[orig_patent_app_number] => 12050719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050719
Method of manufacturing semiconductor device and semiconductor device Mar 17, 2008 Issued
Array ( [id] => 4879844 [patent_doc_number] => 20080153227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/041949 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4420 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153227.pdf [firstpage_image] =>[orig_patent_app_number] => 12041949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041949
NAND flash memory device and method of manufacturing the same Mar 3, 2008 Issued
Array ( [id] => 243232 [patent_doc_number] => 07588966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Chip mounting with flowable layer' [patent_app_type] => utility [patent_app_number] => 12/042144 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2293 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/588/07588966.pdf [firstpage_image] =>[orig_patent_app_number] => 12042144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042144
Chip mounting with flowable layer Mar 3, 2008 Issued
Array ( [id] => 8244826 [patent_doc_number] => 08202750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Method of manufacturing semiconductor device, semiconductor laser, optical pickup, and optical disk device with nitride type group III-V compound semiconductor layer' [patent_app_type] => utility [patent_app_number] => 12/038329 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 67 [patent_no_of_words] => 16670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/202/08202750.pdf [firstpage_image] =>[orig_patent_app_number] => 12038329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038329
Method of manufacturing semiconductor device, semiconductor laser, optical pickup, and optical disk device with nitride type group III-V compound semiconductor layer Feb 26, 2008 Issued
Array ( [id] => 5361113 [patent_doc_number] => 20090035907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/035829 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6882 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035907.pdf [firstpage_image] =>[orig_patent_app_number] => 12035829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035829
METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY Feb 21, 2008 Abandoned
Array ( [id] => 4723836 [patent_doc_number] => 20080203377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES BY IMPLANTING METAL IONS INTO GRAIN BOUNDARIES OF VARIABLE RESISTANCE LAYERS, AND RELATED DEVICES' [patent_app_type] => utility [patent_app_number] => 12/035169 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203377.pdf [firstpage_image] =>[orig_patent_app_number] => 12035169 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035169
Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers Feb 20, 2008 Issued
Array ( [id] => 5425838 [patent_doc_number] => 20090085148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES' [patent_app_type] => utility [patent_app_number] => 12/031909 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085148.pdf [firstpage_image] =>[orig_patent_app_number] => 12031909 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031909
MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES Feb 14, 2008 Abandoned
Array ( [id] => 4785621 [patent_doc_number] => 20080138950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Method To Increase Charge Retention Of Non-Volatile Memory Manufactured In A Single-Gate Logic Process' [patent_app_type] => utility [patent_app_number] => 12/021229 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5449 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20080138950.pdf [firstpage_image] =>[orig_patent_app_number] => 12021229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/021229
Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process Jan 27, 2008 Issued
Array ( [id] => 42579 [patent_doc_number] => 07781279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method for manufacturing a memory' [patent_app_type] => utility [patent_app_number] => 12/018209 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2449 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781279.pdf [firstpage_image] =>[orig_patent_app_number] => 12018209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018209
Method for manufacturing a memory Jan 22, 2008 Issued
Array ( [id] => 83443 [patent_doc_number] => 07741174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures' [patent_app_type] => utility [patent_app_number] => 12/017449 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6769 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741174.pdf [firstpage_image] =>[orig_patent_app_number] => 12017449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017449
Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures Jan 21, 2008 Issued
Array ( [id] => 4839914 [patent_doc_number] => 20080280400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/969990 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2708 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20080280400.pdf [firstpage_image] =>[orig_patent_app_number] => 11969990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969990
Method for manufacturing semiconductor device Jan 6, 2008 Issued
Array ( [id] => 5432183 [patent_doc_number] => 20090166769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/968099 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2718 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166769.pdf [firstpage_image] =>[orig_patent_app_number] => 11968099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968099
Methods for fabricating PMOS metal gate structures Dec 30, 2007 Issued
Array ( [id] => 4752631 [patent_doc_number] => 20080160706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/964108 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3071 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160706.pdf [firstpage_image] =>[orig_patent_app_number] => 11964108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964108
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Dec 25, 2007 Abandoned
Array ( [id] => 4749096 [patent_doc_number] => 20080157167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/963588 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2038 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157167.pdf [firstpage_image] =>[orig_patent_app_number] => 11963588 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963588
Flash memory device Dec 20, 2007 Issued
Array ( [id] => 7522983 [patent_doc_number] => 08026139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Method of fabricating a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/962058 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2972 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/026/08026139.pdf [firstpage_image] =>[orig_patent_app_number] => 11962058 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962058
Method of fabricating a non-volatile memory device Dec 19, 2007 Issued
Array ( [id] => 5542768 [patent_doc_number] => 20090152645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/959409 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 8081 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20090152645.pdf [firstpage_image] =>[orig_patent_app_number] => 11959409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959409
Methods for isolating portions of a loop of pitch-multiplied material and related structures Dec 17, 2007 Issued
Array ( [id] => 8446779 [patent_doc_number] => 08288834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-16 [patent_title] => 'Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/002486 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2022 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12002486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/002486
Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devices Dec 16, 2007 Issued
Array ( [id] => 4546667 [patent_doc_number] => 07960236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Phosphorus containing Si epitaxial layers in N-type source/drain junctions' [patent_app_type] => utility [patent_app_number] => 11/957820 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960236.pdf [firstpage_image] =>[orig_patent_app_number] => 11957820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957820
Phosphorus containing Si epitaxial layers in N-type source/drain junctions Dec 16, 2007 Issued
Array ( [id] => 4745753 [patent_doc_number] => 20080090355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'MANUFACTURING METHOD OF FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/955348 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5855 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090355.pdf [firstpage_image] =>[orig_patent_app_number] => 11955348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955348
MANUFACTURING METHOD OF FLASH MEMORY Dec 11, 2007 Abandoned
Array ( [id] => 4866933 [patent_doc_number] => 20080145992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Method of Manufacturing a Semiconductor Device Having Reduced N/P or P/N Junction Crystal Disorder' [patent_app_type] => utility [patent_app_number] => 11/951448 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3792 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20080145992.pdf [firstpage_image] =>[orig_patent_app_number] => 11951448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951448
Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder Dec 5, 2007 Issued
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