Thanhha S. Pham

Array ( [id] => 7442966 [patent_doc_number] => 20040185650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'METAL BONDING METHOD FOR SEMICONDUCTOR CIRCUIT COMPONENTS EMPLOYING PRESCRIBED FEEDS OF METAL BALLS' [patent_app_type] => new [patent_app_number] => 10/249572 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185650.pdf [firstpage_image] =>[orig_patent_app_number] => 10249572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7429304 [patent_doc_number] => 20040209450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Method of manufacturing a semiconductor device for reducing resistance of a CoSi2 layer' [patent_app_type] => new [patent_app_number] => 10/414095 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1804 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209450.pdf [firstpage_image] =>[orig_patent_app_number] => 10414095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7609911 [patent_doc_number] => 06998275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Hydrogen-less CVD TiN process for FeRAM VIA0 barrier application' [patent_app_type] => utility [patent_app_number] => 10/410091 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9421 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998275.pdf [firstpage_image] =>[orig_patent_app_number] => 10410091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7184242 [patent_doc_number] => 20040203223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects' [patent_app_type] => new [patent_app_number] => 10/410122 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6141 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203223.pdf [firstpage_image] =>[orig_patent_app_number] => 10410122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7008776 [patent_doc_number] => 20050062492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'High density integrated circuit apparatus, test probe and methods of use thereof' [patent_app_type] => utility [patent_app_number] => 10/408200 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5004 [patent_no_of_claims] => 300 [patent_no_of_ind_claims] => 46 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062492.pdf [firstpage_image] =>[orig_patent_app_number] => 10408200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 948787 [patent_doc_number] => 06962823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices' [patent_app_type] => utility [patent_app_number] => 10/405992 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 27907 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/962/06962823.pdf [firstpage_image] =>[orig_patent_app_number] => 10405992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 975493 [patent_doc_number] => 06933224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method of fabricating integrated circuitry' [patent_app_type] => utility [patent_app_number] => 10/402471 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3190 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933224.pdf [firstpage_image] =>[orig_patent_app_number] => 10402471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6730297 [patent_doc_number] => 20030186487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product' [patent_app_type] => new [patent_app_number] => 10/402811 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186487.pdf [firstpage_image] =>[orig_patent_app_number] => 10402811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 749787 [patent_doc_number] => 07022619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method for fabricating electronic device' [patent_app_type] => utility [patent_app_number] => 10/395182 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 58 [patent_no_of_words] => 14830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022619.pdf [firstpage_image] =>[orig_patent_app_number] => 10395182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6829972 [patent_doc_number] => 20030181030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method of forming an intermetal dielectric layer' [patent_app_type] => new [patent_app_number] => 10/390691 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20030181030.pdf [firstpage_image] =>[orig_patent_app_number] => 10390691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7281218 [patent_doc_number] => 20040063595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Composition for stripping photoresist and method of preparing the same' [patent_app_type] => new [patent_app_number] => 10/384711 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6831 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063595.pdf [firstpage_image] =>[orig_patent_app_number] => 10384711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673233 [patent_doc_number] => 20040180546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Polish method for semiconductor device planarization' [patent_app_type] => new [patent_app_number] => 10/384641 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2658 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180546.pdf [firstpage_image] =>[orig_patent_app_number] => 10384641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7406261 [patent_doc_number] => 20040175845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method of forming a flux concentrating layer of a magnetic device' [patent_app_type] => new [patent_app_number] => 10/377952 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175845.pdf [firstpage_image] =>[orig_patent_app_number] => 10377952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6834835 [patent_doc_number] => 20030162381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'LEAD-FREE BUMP FABRICATION PROCESS' [patent_app_type] => new [patent_app_number] => 10/248882 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2299 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20030162381.pdf [firstpage_image] =>[orig_patent_app_number] => 10248882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465588 [patent_doc_number] => 20040166661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Method for forming copper bump antioxidation surface' [patent_app_type] => new [patent_app_number] => 10/370827 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3071 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166661.pdf [firstpage_image] =>[orig_patent_app_number] => 10370827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465589 [patent_doc_number] => 20040166662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'MEMS wafer level chip scale package' [patent_app_type] => new [patent_app_number] => 10/371042 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166662.pdf [firstpage_image] =>[orig_patent_app_number] => 10371042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7392244 [patent_doc_number] => 20040017646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Electrochemical capacitor and method for its preparation' [patent_app_type] => new [patent_app_number] => 10/368014 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5837 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017646.pdf [firstpage_image] =>[orig_patent_app_number] => 10368014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6843254 [patent_doc_number] => 20030148601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Fill material for dual damascene processes' [patent_app_type] => new [patent_app_number] => 10/366963 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10877 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148601.pdf [firstpage_image] =>[orig_patent_app_number] => 10366963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7620072 [patent_doc_number] => 06943111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Barrier free copper interconnect by multi-layer copper seed' [patent_app_type] => utility [patent_app_number] => 10/361732 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2592 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943111.pdf [firstpage_image] =>[orig_patent_app_number] => 10361732 [rel_patent_id] =>[rel_patent_doc_number] =>)