Thanhha S. Pham

Array ( [id] => 4733936 [patent_doc_number] => 20080050915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/882663 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3396 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050915.pdf [firstpage_image] =>[orig_patent_app_number] => 11882663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 22146 [patent_doc_number] => 07799608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Die stacking apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/832519 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799608.pdf [firstpage_image] =>[orig_patent_app_number] => 11832519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4619161 [patent_doc_number] => 07998880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties' [patent_app_type] => utility [patent_app_number] => 11/830425 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/998/07998880.pdf [firstpage_image] =>[orig_patent_app_number] => 11830425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 256333 [patent_doc_number] => 07576006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-18 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/888323 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 17501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/576/07576006.pdf [firstpage_image] =>[orig_patent_app_number] => 11888323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5337442 [patent_doc_number] => 20090053906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Semiconductor Device Producing Method and Substrate Processing Apparatus' [patent_app_type] => utility [patent_app_number] => 12/087779 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8456 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20090053906.pdf [firstpage_image] =>[orig_patent_app_number] => 12087779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5016280 [patent_doc_number] => 20070259489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Method of forming transistor structure having stressed regions of opposite types' [patent_app_type] => utility [patent_app_number] => 11/879065 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259489.pdf [firstpage_image] =>[orig_patent_app_number] => 11879065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 53853 [patent_doc_number] => 07767558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method of crystallizing amorphous silicon and device fabricated using the same' [patent_app_type] => utility [patent_app_number] => 11/822297 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3271 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767558.pdf [firstpage_image] =>[orig_patent_app_number] => 11822297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5210505 [patent_doc_number] => 20070249089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method of making circuitized substrate with internal organic memory device' [patent_app_type] => utility [patent_app_number] => 11/808596 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8250 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249089.pdf [firstpage_image] =>[orig_patent_app_number] => 11808596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8270081 [patent_doc_number] => 08211584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Metal separator for fuel cell and fuel cell stack having the same' [patent_app_type] => utility [patent_app_number] => 12/445576 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12445576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5225152 [patent_doc_number] => 20070254418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Methods of fabricating nitride-based transistors with a cap layer and a recessed gate' [patent_app_type] => utility [patent_app_number] => 11/810026 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7192 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254418.pdf [firstpage_image] =>[orig_patent_app_number] => 11810026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 83543 [patent_doc_number] => 07741215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/809478 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6685 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741215.pdf [firstpage_image] =>[orig_patent_app_number] => 11809478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4752678 [patent_doc_number] => 20080160753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Method of forming metal wire in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/801498 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160753.pdf [firstpage_image] =>[orig_patent_app_number] => 11801498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5046142 [patent_doc_number] => 20070264815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/797249 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5039 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264815.pdf [firstpage_image] =>[orig_patent_app_number] => 11797249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 236552 [patent_doc_number] => 07595533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Thin film semiconductor device and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/740226 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 16057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595533.pdf [firstpage_image] =>[orig_patent_app_number] => 11740226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5569895 [patent_doc_number] => 20090253273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'METHOD OF HEAT-TREATING SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 12/305180 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20090253273.pdf [firstpage_image] =>[orig_patent_app_number] => 12305180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5113113 [patent_doc_number] => 20070197028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'FORMATION OF BORIDE BARRIER LAYERS USING CHEMISORPTION TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/739549 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4579 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197028.pdf [firstpage_image] =>[orig_patent_app_number] => 11739549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5113112 [patent_doc_number] => 20070197027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'FORMATION OF BORIDE BARRIER LAYERS USING CHEMISORPTION TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/739545 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4577 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197027.pdf [firstpage_image] =>[orig_patent_app_number] => 11739545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026290 [patent_doc_number] => 20070267736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/734996 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267736.pdf [firstpage_image] =>[orig_patent_app_number] => 11734996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5110498 [patent_doc_number] => 20070194413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method for manufacturing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/783765 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194413.pdf [firstpage_image] =>[orig_patent_app_number] => 11783765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 359640 [patent_doc_number] => 07485519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'After gate fabrication of field effect transistor having tensile and compressive regions' [patent_app_type] => utility [patent_app_number] => 11/693786 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4706 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485519.pdf [firstpage_image] =>[orig_patent_app_number] => 11693786 [rel_patent_id] =>[rel_patent_doc_number] =>)