Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 908208 [patent_doc_number] => 07332774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Multiple-gate MOS transistor and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/727268 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4733 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332774.pdf [firstpage_image] =>[orig_patent_app_number] => 11727268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727268
Multiple-gate MOS transistor and a method of manufacturing the same Mar 25, 2007 Issued
Array ( [id] => 122750 [patent_doc_number] => 07704873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/726363 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 17461 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704873.pdf [firstpage_image] =>[orig_patent_app_number] => 11726363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726363
Protective self-aligned buffer layers for damascene interconnects Mar 19, 2007 Issued
Array ( [id] => 102090 [patent_doc_number] => 07727880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/709294 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 15101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727880.pdf [firstpage_image] =>[orig_patent_app_number] => 11709294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709294
Protective self-aligned buffer layers for damascene interconnects Feb 19, 2007 Issued
Array ( [id] => 102091 [patent_doc_number] => 07727881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/709293 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 15088 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727881.pdf [firstpage_image] =>[orig_patent_app_number] => 11709293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709293
Protective self-aligned buffer layers for damascene interconnects Feb 19, 2007 Issued
Array ( [id] => 303966 [patent_doc_number] => 07535106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate' [patent_app_type] => utility [patent_app_number] => 11/657280 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 42 [patent_no_of_words] => 28902 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535106.pdf [firstpage_image] =>[orig_patent_app_number] => 11657280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657280
Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate Jan 23, 2007 Issued
Array ( [id] => 5256799 [patent_doc_number] => 20070210431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 11/657703 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4122 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210431.pdf [firstpage_image] =>[orig_patent_app_number] => 11657703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657703
Support with integrated deposit of gas absorbing material for manufacturing microelectronic, microoptoelectronic or micromechanical devices Jan 22, 2007 Issued
Array ( [id] => 4651605 [patent_doc_number] => 20080038861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 11/657706 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038861.pdf [firstpage_image] =>[orig_patent_app_number] => 11657706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657706
Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices Jan 22, 2007 Issued
Array ( [id] => 4971408 [patent_doc_number] => 20070111410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'HIGH MOBILITY PLANE FINFETS WITH EQUAL DRIVE STRENGTH' [patent_app_type] => utility [patent_app_number] => 11/622169 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111410.pdf [firstpage_image] =>[orig_patent_app_number] => 11622169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622169
High mobility plane FinFETs with equal drive strength Jan 10, 2007 Issued
Array ( [id] => 7689457 [patent_doc_number] => 20070105241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Ferromagnetic liner for conductive lines of magnetic memory cells' [patent_app_type] => utility [patent_app_number] => 11/644792 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7894 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105241.pdf [firstpage_image] =>[orig_patent_app_number] => 11644792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644792
Ferromagnetic liner for conductive lines of magnetic memory cells Dec 21, 2006 Issued
Array ( [id] => 6470419 [patent_doc_number] => 20100040911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'FUEL CELL FLOW FIELD HAVING STRONG, CHEMICALLY STABLE METAL BIPOLAR PLATES' [patent_app_type] => utility [patent_app_number] => 12/514507 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20100040911.pdf [firstpage_image] =>[orig_patent_app_number] => 12514507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/514507
Fuel cell flow field having strong, chemically stable metal bipolar plates Dec 7, 2006 Issued
Array ( [id] => 4833513 [patent_doc_number] => 20080132060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'CONTACT BARRIER LAYER DEPOSITION PROCESS' [patent_app_type] => utility [patent_app_number] => 11/565355 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5568 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20080132060.pdf [firstpage_image] =>[orig_patent_app_number] => 11565355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565355
CONTACT BARRIER LAYER DEPOSITION PROCESS Nov 29, 2006 Abandoned
Array ( [id] => 5077038 [patent_doc_number] => 20070120262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/564175 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120262.pdf [firstpage_image] =>[orig_patent_app_number] => 11564175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564175
Semiconductor device and method for manufacturing the same Nov 27, 2006 Issued
Array ( [id] => 4825904 [patent_doc_number] => 20080124859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques' [patent_app_type] => utility [patent_app_number] => 11/563476 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1973 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124859.pdf [firstpage_image] =>[orig_patent_app_number] => 11563476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563476
Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques Nov 26, 2006 Abandoned
Array ( [id] => 4820756 [patent_doc_number] => 20080122042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'APPLICATIONS OF POLYCRYSTALLINE WAFERS' [patent_app_type] => utility [patent_app_number] => 11/563626 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3099 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122042.pdf [firstpage_image] =>[orig_patent_app_number] => 11563626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563626
APPLICATIONS OF POLYCRYSTALLINE WAFERS Nov 26, 2006 Abandoned
Array ( [id] => 5157396 [patent_doc_number] => 20070170440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Wafer encapsulated microelectromechanical structure and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/600860 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 210 [patent_figures_cnt] => 210 [patent_no_of_words] => 18533 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170440.pdf [firstpage_image] =>[orig_patent_app_number] => 11600860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600860
Wafer encapsulated microelectromechanical structure and method of manufacturing same Nov 15, 2006 Abandoned
Array ( [id] => 864764 [patent_doc_number] => 07368395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Method for fabricating a nano-imprinting mold' [patent_app_type] => utility [patent_app_number] => 11/601084 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368395.pdf [firstpage_image] =>[orig_patent_app_number] => 11601084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601084
Method for fabricating a nano-imprinting mold Nov 15, 2006 Issued
Array ( [id] => 281750 [patent_doc_number] => 07553750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Method for fabricating electrical conductive structure of circuit board' [patent_app_type] => utility [patent_app_number] => 11/559576 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 2759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553750.pdf [firstpage_image] =>[orig_patent_app_number] => 11559576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559576
Method for fabricating electrical conductive structure of circuit board Nov 13, 2006 Issued
Array ( [id] => 5043792 [patent_doc_number] => 20070262463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements' [patent_app_type] => utility [patent_app_number] => 11/585655 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20070262463.pdf [firstpage_image] =>[orig_patent_app_number] => 11585655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585655
Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements Oct 23, 2006 Abandoned
Array ( [id] => 5031673 [patent_doc_number] => 20070096212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/583846 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8848 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096212.pdf [firstpage_image] =>[orig_patent_app_number] => 11583846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583846
Semiconductor device and method for fabricating the same Oct 19, 2006 Abandoned
Array ( [id] => 281760 [patent_doc_number] => 07553760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Sub-lithographic nano interconnect structures, and method for forming same' [patent_app_type] => utility [patent_app_number] => 11/550966 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 8000 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553760.pdf [firstpage_image] =>[orig_patent_app_number] => 11550966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550966
Sub-lithographic nano interconnect structures, and method for forming same Oct 18, 2006 Issued
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