
Thanhha S. Pham
Examiner (ID: 17114, Phone: (571)272-1696 , Office: P/2819 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2812, 2813, 2819, 2894 |
| Total Applications | 1792 |
| Issued Applications | 1465 |
| Pending Applications | 114 |
| Abandoned Applications | 231 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1205669
[patent_doc_number] => 06716742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics'
[patent_app_type] => B2
[patent_app_number] => 10/292205
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4725
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/716/06716742.pdf
[firstpage_image] =>[orig_patent_app_number] => 10292205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292205 | Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics | Nov 11, 2002 | Issued |
Array
(
[id] => 6696942
[patent_doc_number] => 20030109136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/287549
[patent_app_country] => US
[patent_app_date] => 2002-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 11935
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20030109136.pdf
[firstpage_image] =>[orig_patent_app_number] => 10287549
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/287549 | Semiconductor device and method of manufacturing the same | Nov 4, 2002 | Issued |
Array
(
[id] => 1299850
[patent_doc_number] => 06624075
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Method of reducing electromigration in a copper line by Zinc-Doping of a copper surface from an electroplated copper-zinc alloy thin film and a semiconductor device thereby formed'
[patent_app_type] => B1
[patent_app_number] => 10/288862
[patent_app_country] => US
[patent_app_date] => 2002-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 6860
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 556
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/624/06624075.pdf
[firstpage_image] =>[orig_patent_app_number] => 10288862
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/288862 | Method of reducing electromigration in a copper line by Zinc-Doping of a copper surface from an electroplated copper-zinc alloy thin film and a semiconductor device thereby formed | Nov 4, 2002 | Issued |
Array
(
[id] => 6829973
[patent_doc_number] => 20030181031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/286812
[patent_app_country] => US
[patent_app_date] => 2002-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2780
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20030181031.pdf
[firstpage_image] =>[orig_patent_app_number] => 10286812
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/286812 | Method for manufacturing a semiconductor device | Nov 3, 2002 | Abandoned |
Array
(
[id] => 7383479
[patent_doc_number] => 20040082169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Deposition of barrier metal in damascene interconnects using metal carbonyl'
[patent_app_type] => new
[patent_app_number] => 10/282388
[patent_app_country] => US
[patent_app_date] => 2002-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2876
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20040082169.pdf
[firstpage_image] =>[orig_patent_app_number] => 10282388
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282388 | Deposition of barrier metal in damascene interconnects using metal carbonyl | Oct 28, 2002 | Abandoned |
Array
(
[id] => 7167336
[patent_doc_number] => 20040077160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Method to control dimensions of features on a substrate with an organic anti-reflective coating'
[patent_app_type] => new
[patent_app_number] => 10/277461
[patent_app_country] => US
[patent_app_date] => 2002-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3074
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20040077160.pdf
[firstpage_image] =>[orig_patent_app_number] => 10277461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/277461 | Method to control dimensions of features on a substrate with an organic anti-reflective coating | Oct 21, 2002 | Abandoned |
Array
(
[id] => 774779
[patent_doc_number] => 07002201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/274112
[patent_app_country] => US
[patent_app_date] => 2002-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 81
[patent_no_of_words] => 9023
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/002/07002201.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274112
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274112 | Semiconductor device and manufacturing method thereof | Oct 20, 2002 | Issued |
Array
(
[id] => 6664280
[patent_doc_number] => 20030203606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/273151
[patent_app_country] => US
[patent_app_date] => 2002-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5290
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20030203606.pdf
[firstpage_image] =>[orig_patent_app_number] => 10273151
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273151 | Method for manufacturing a semiconductor device | Oct 17, 2002 | Issued |
Array
(
[id] => 7167088
[patent_doc_number] => 20040077107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Method of making nanoscopic tunnel'
[patent_app_type] => new
[patent_app_number] => 10/272892
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5715
[patent_no_of_claims] => 58
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20040077107.pdf
[firstpage_image] =>[orig_patent_app_number] => 10272892
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/272892 | Method of making nanoscopic tunnel | Oct 16, 2002 | Abandoned |
Array
(
[id] => 1031094
[patent_doc_number] => 06878646
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-12
[patent_title] => 'Method to control critical dimension of a hard masked pattern'
[patent_app_type] => utility
[patent_app_number] => 10/272082
[patent_app_country] => US
[patent_app_date] => 2002-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4827
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/878/06878646.pdf
[firstpage_image] =>[orig_patent_app_number] => 10272082
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/272082 | Method to control critical dimension of a hard masked pattern | Oct 15, 2002 | Issued |
Array
(
[id] => 1050097
[patent_doc_number] => 06861376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-01
[patent_title] => 'Photoresist scum free process for via first dual damascene process'
[patent_app_type] => utility
[patent_app_number] => 10/268587
[patent_app_country] => US
[patent_app_date] => 2002-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 5796
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/861/06861376.pdf
[firstpage_image] =>[orig_patent_app_number] => 10268587
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/268587 | Photoresist scum free process for via first dual damascene process | Oct 9, 2002 | Issued |
Array
(
[id] => 728237
[patent_doc_number] => 07041516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Multi chip module assembly'
[patent_app_type] => utility
[patent_app_number] => 10/268361
[patent_app_country] => US
[patent_app_date] => 2002-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2287
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/041/07041516.pdf
[firstpage_image] =>[orig_patent_app_number] => 10268361
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/268361 | Multi chip module assembly | Oct 9, 2002 | Issued |
Array
(
[id] => 972151
[patent_doc_number] => 06936536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Methods of forming conductive through-wafer vias'
[patent_app_type] => utility
[patent_app_number] => 10/267822
[patent_app_country] => US
[patent_app_date] => 2002-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 3601
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/936/06936536.pdf
[firstpage_image] =>[orig_patent_app_number] => 10267822
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267822 | Methods of forming conductive through-wafer vias | Oct 8, 2002 | Issued |
Array
(
[id] => 1138380
[patent_doc_number] => 06780751
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Method for eliminating voiding in plated solder'
[patent_app_type] => B2
[patent_app_number] => 10/267453
[patent_app_country] => US
[patent_app_date] => 2002-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 21
[patent_no_of_words] => 4432
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/780/06780751.pdf
[firstpage_image] =>[orig_patent_app_number] => 10267453
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267453 | Method for eliminating voiding in plated solder | Oct 8, 2002 | Issued |
Array
(
[id] => 6813749
[patent_doc_number] => 20030073299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Method of forming through-hole or recess in silicon substrate'
[patent_app_type] => new
[patent_app_number] => 10/266730
[patent_app_country] => US
[patent_app_date] => 2002-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5386
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20030073299.pdf
[firstpage_image] =>[orig_patent_app_number] => 10266730
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/266730 | Method of forming through-hole or recess in silicon substrate | Oct 7, 2002 | Issued |
Array
(
[id] => 616400
[patent_doc_number] => 07144811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Method of forming a protective layer over Cu filled semiconductor features'
[patent_app_type] => utility
[patent_app_number] => 10/264462
[patent_app_country] => US
[patent_app_date] => 2002-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2726
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/144/07144811.pdf
[firstpage_image] =>[orig_patent_app_number] => 10264462
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/264462 | Method of forming a protective layer over Cu filled semiconductor features | Oct 2, 2002 | Issued |
Array
(
[id] => 742659
[patent_doc_number] => 07025795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Electrode for electrolytic capacitor, electrolytic capacitor, and manufacturing method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/262613
[patent_app_country] => US
[patent_app_date] => 2002-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4155
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/025/07025795.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262613
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262613 | Electrode for electrolytic capacitor, electrolytic capacitor, and manufacturing method therefor | Oct 1, 2002 | Issued |
Array
(
[id] => 993636
[patent_doc_number] => 06916735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-12
[patent_title] => 'Method for forming aerial metallic wiring on semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 10/259501
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 18
[patent_no_of_words] => 3734
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/916/06916735.pdf
[firstpage_image] =>[orig_patent_app_number] => 10259501
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/259501 | Method for forming aerial metallic wiring on semiconductor substrate | Sep 29, 2002 | Issued |
Array
(
[id] => 1318508
[patent_doc_number] => 06605535
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-12
[patent_title] => 'Method of filling trenches using vapor-liquid-solid mechanism'
[patent_app_type] => B1
[patent_app_number] => 10/256051
[patent_app_country] => US
[patent_app_date] => 2002-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3404
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/605/06605535.pdf
[firstpage_image] =>[orig_patent_app_number] => 10256051
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/256051 | Method of filling trenches using vapor-liquid-solid mechanism | Sep 25, 2002 | Issued |
Array
(
[id] => 7629791
[patent_doc_number] => 06818565
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Gate insulator pre-clean procedure'
[patent_app_type] => B1
[patent_app_number] => 10/253270
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2085
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818565.pdf
[firstpage_image] =>[orig_patent_app_number] => 10253270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/253270 | Gate insulator pre-clean procedure | Sep 23, 2002 | Issued |