Search

Thanhha S. Pham

Examiner (ID: 11625)

Most Active Art Unit
2819
Art Unit(s)
2813, 2819, 2812, 2894
Total Applications
1754
Issued Applications
1445
Pending Applications
106
Abandoned Applications
230

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19094045 [patent_doc_number] => 11955512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-09 [patent_title] => Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/552266 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 95 [patent_no_of_words] => 45596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552266
Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication Dec 14, 2021 Issued
Array ( [id] => 19294720 [patent_doc_number] => 12034086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Trench capacitors with continuous dielectric layer and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/552269 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 95 [patent_no_of_words] => 45604 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552269
Trench capacitors with continuous dielectric layer and methods of fabrication Dec 14, 2021 Issued
Array ( [id] => 19108763 [patent_doc_number] => 11961877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-16 [patent_title] => Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures [patent_app_type] => utility [patent_app_number] => 17/550899 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 95 [patent_no_of_words] => 45532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550899
Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures Dec 13, 2021 Issued
Array ( [id] => 18408900 [patent_doc_number] => 20230170253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => DUAL-DAMASCENE FAV INTERCONNECTS WITH DIELECTRIC PLUG [patent_app_type] => utility [patent_app_number] => 17/457238 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457238
Dual-damascene fav interconnects with dielectric plug Nov 30, 2021 Issued
Array ( [id] => 19079491 [patent_doc_number] => 11948868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Compact leadframe package [patent_app_type] => utility [patent_app_number] => 17/537318 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3600 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537318
Compact leadframe package Nov 28, 2021 Issued
Array ( [id] => 18919143 [patent_doc_number] => 11881431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Anti-fuse with laterally extended liner [patent_app_type] => utility [patent_app_number] => 17/456016 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 6382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456016
Anti-fuse with laterally extended liner Nov 21, 2021 Issued
Array ( [id] => 18595151 [patent_doc_number] => 11744073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor device and apparatus of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/530915 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 11843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530915
Semiconductor device and apparatus of manufacturing the same Nov 18, 2021 Issued
Array ( [id] => 17764820 [patent_doc_number] => 20220238433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/453197 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453197
Semiconductor devices Nov 1, 2021 Issued
Array ( [id] => 17402872 [patent_doc_number] => 20220044963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE HAVING VOID BETWEEN BONDED WAFERS [patent_app_type] => utility [patent_app_number] => 17/511211 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511211
Method for preparing semiconductor structure having void between bonded wafers Oct 25, 2021 Issued
Array ( [id] => 17509151 [patent_doc_number] => 20220102254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CHIP PACKAGING METHOD AND CHIP STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/508335 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508335
CHIP PACKAGING METHOD AND CHIP STRUCTURE Oct 21, 2021 Pending
Array ( [id] => 19918595 [patent_doc_number] => 12293971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Semiconductor structure and formation method thereof [patent_app_type] => utility [patent_app_number] => 17/451667 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451667
Semiconductor structure and formation method thereof Oct 20, 2021 Issued
Array ( [id] => 17448196 [patent_doc_number] => 20220068701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/501523 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501523
Methods of performing chemical-mechanical polishing process in semiconductor devices Oct 13, 2021 Issued
Array ( [id] => 18564730 [patent_doc_number] => 11730000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => 3-dimensional nor string arrays in segmented stacks [patent_app_type] => utility [patent_app_number] => 17/493502 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1436 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493502
3-dimensional nor string arrays in segmented stacks Oct 3, 2021 Issued
Array ( [id] => 18721523 [patent_doc_number] => 11798880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Electronic device and method of fabricating an electronic device [patent_app_type] => utility [patent_app_number] => 17/486868 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486868
Electronic device and method of fabricating an electronic device Sep 26, 2021 Issued
Array ( [id] => 18782226 [patent_doc_number] => 11823992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Semiconductor device with uneven electrode surface and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/484485 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9740 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484485
Semiconductor device with uneven electrode surface and method for fabricating the same Sep 23, 2021 Issued
Array ( [id] => 18281712 [patent_doc_number] => 20230097184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => INTEGRATED CIRCUITS WITH HIGH DIELECTRIC CONSTANT INTERFACIAL LAYERING [patent_app_type] => utility [patent_app_number] => 17/485310 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485310
INTEGRATED CIRCUITS WITH HIGH DIELECTRIC CONSTANT INTERFACIAL LAYERING Sep 23, 2021 Pending
Array ( [id] => 18281712 [patent_doc_number] => 20230097184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => INTEGRATED CIRCUITS WITH HIGH DIELECTRIC CONSTANT INTERFACIAL LAYERING [patent_app_type] => utility [patent_app_number] => 17/485310 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485310
INTEGRATED CIRCUITS WITH HIGH DIELECTRIC CONSTANT INTERFACIAL LAYERING Sep 23, 2021 Pending
Array ( [id] => 20405569 [patent_doc_number] => 12495559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Capacitor with dual dielectric layers [patent_app_type] => utility [patent_app_number] => 17/483795 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2465 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483795
Capacitor with dual dielectric layers Sep 22, 2021 Issued
Array ( [id] => 18269741 [patent_doc_number] => 20230090983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => LINE FORMATION WITH CUT-FIRST TIP DEFINITION [patent_app_type] => utility [patent_app_number] => 17/482939 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482939
Line formation with cut-first tip definition Sep 22, 2021 Issued
Array ( [id] => 19277284 [patent_doc_number] => 12027416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => BEOL etch stop layer without capacitance penalty [patent_app_type] => utility [patent_app_number] => 17/476521 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4058 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476521
BEOL etch stop layer without capacitance penalty Sep 15, 2021 Issued
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