Search

Thanhnga B. Truong

Examiner (ID: 2062)

Most Active Art Unit
2438
Art Unit(s)
2435, 2135, 2438, 2498
Total Applications
886
Issued Applications
752
Pending Applications
24
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5628852 [patent_doc_number] => 20060145320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Embedded heat spreader' [patent_app_type] => utility [patent_app_number] => 11/027291 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1875 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145320.pdf [firstpage_image] =>[orig_patent_app_number] => 11027291 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027291
Embedded heat spreader Dec 29, 2004 Issued
Array ( [id] => 5652891 [patent_doc_number] => 20060138626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Microelectronic packages using a ceramic substrate having a window and a conductive surface region' [patent_app_type] => utility [patent_app_number] => 11/025432 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7473 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138626.pdf [firstpage_image] =>[orig_patent_app_number] => 11025432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025432
Microelectronic packages using a ceramic substrate having a window and a conductive surface region Dec 28, 2004 Abandoned
Array ( [id] => 7101443 [patent_doc_number] => 20050104169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Stress-free lead frame' [patent_app_type] => utility [patent_app_number] => 11/022071 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104169.pdf [firstpage_image] =>[orig_patent_app_number] => 11022071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022071
Stress-free lead frame Dec 22, 2004 Issued
Array ( [id] => 865583 [patent_doc_number] => 07368825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Power semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/019741 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2567 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368825.pdf [firstpage_image] =>[orig_patent_app_number] => 11019741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019741
Power semiconductor device Dec 22, 2004 Issued
Array ( [id] => 7002489 [patent_doc_number] => 20050167802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/019242 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7748 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167802.pdf [firstpage_image] =>[orig_patent_app_number] => 11019242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019242
Semiconductor device Dec 22, 2004 Abandoned
Array ( [id] => 6936591 [patent_doc_number] => 20050110152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method for forming openings in low dielectric constant material layer' [patent_app_type] => utility [patent_app_number] => 11/021411 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3325 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110152.pdf [firstpage_image] =>[orig_patent_app_number] => 11021411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021411
Method for forming openings in low dielectric constant material layer Dec 22, 2004 Abandoned
Array ( [id] => 7183379 [patent_doc_number] => 20050161782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'HYBRID INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 10/905251 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161782.pdf [firstpage_image] =>[orig_patent_app_number] => 10905251 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905251
HYBRID INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME Dec 21, 2004 Abandoned
Array ( [id] => 6903478 [patent_doc_number] => 20050098873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Stacked module systems and methods' [patent_app_type] => utility [patent_app_number] => 11/015521 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4265 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098873.pdf [firstpage_image] =>[orig_patent_app_number] => 11015521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015521
Stacked module systems and methods Dec 16, 2004 Abandoned
Array ( [id] => 7599483 [patent_doc_number] => 07582965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Electronic device and method for bonding an electronic device' [patent_app_type] => utility [patent_app_number] => 10/586942 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1366 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/582/07582965.pdf [firstpage_image] =>[orig_patent_app_number] => 10586942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/586942
Electronic device and method for bonding an electronic device Dec 13, 2004 Issued
Array ( [id] => 830492 [patent_doc_number] => 07400047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Integrated circuit with stacked-die configuration utilizing substrate conduction' [patent_app_type] => utility [patent_app_number] => 11/010721 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4510 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400047.pdf [firstpage_image] =>[orig_patent_app_number] => 11010721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010721
Integrated circuit with stacked-die configuration utilizing substrate conduction Dec 12, 2004 Issued
Array ( [id] => 5233913 [patent_doc_number] => 20070126068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Microcomponent comprising a hermetically-sealed cavity and a plug, and method of producing one such microcomponent' [patent_app_type] => utility [patent_app_number] => 10/582521 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1643 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126068.pdf [firstpage_image] =>[orig_patent_app_number] => 10582521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/582521
Microcomponent comprising a hermetically-sealed cavity and a plug, and method of producing one such microcomponent Dec 12, 2004 Issued
Array ( [id] => 5898316 [patent_doc_number] => 20060043549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Micro-electronic package structure and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/008972 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4001 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043549.pdf [firstpage_image] =>[orig_patent_app_number] => 11008972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008972
Micro-electronic package structure and method for fabricating the same Dec 12, 2004 Abandoned
Array ( [id] => 4971350 [patent_doc_number] => 20070111352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Wafer with optical control modules in dicing paths' [patent_app_type] => utility [patent_app_number] => 10/584102 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3801 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111352.pdf [firstpage_image] =>[orig_patent_app_number] => 10584102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/584102
Wafer with optical control modules in dicing paths Dec 8, 2004 Issued
Array ( [id] => 428991 [patent_doc_number] => 07268427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Semiconductor package, printed board mounted with the same, and electronic apparatus having the printed board' [patent_app_type] => utility [patent_app_number] => 11/003402 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5904 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268427.pdf [firstpage_image] =>[orig_patent_app_number] => 11003402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003402
Semiconductor package, printed board mounted with the same, and electronic apparatus having the printed board Dec 5, 2004 Issued
Array ( [id] => 5838289 [patent_doc_number] => 20060118947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Thermal expansion compensating flip chip ball grid array package structure' [patent_app_type] => utility [patent_app_number] => 11/002192 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118947.pdf [firstpage_image] =>[orig_patent_app_number] => 11002192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002192
Thermal expansion compensating flip chip ball grid array package structure Dec 2, 2004 Abandoned
Array ( [id] => 5838281 [patent_doc_number] => 20060118939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Stacked electronics for sensors' [patent_app_type] => utility [patent_app_number] => 11/003602 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6119 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118939.pdf [firstpage_image] =>[orig_patent_app_number] => 11003602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003602
Stacked electronics for sensors Dec 2, 2004 Issued
Array ( [id] => 7067045 [patent_doc_number] => 20050242427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'FCBGA package structure' [patent_app_type] => utility [patent_app_number] => 10/997343 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2555 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242427.pdf [firstpage_image] =>[orig_patent_app_number] => 10997343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997343
FCBGA package structure Nov 23, 2004 Abandoned
Array ( [id] => 4997611 [patent_doc_number] => 20070040245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Anisotropic conductive sheet, manufacturing method thereof, and product using the same' [patent_app_type] => utility [patent_app_number] => 10/579342 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 39372 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040245.pdf [firstpage_image] =>[orig_patent_app_number] => 10579342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/579342
Anisotropic conductive sheet, manufacturing method thereof, and product using the same Nov 14, 2004 Abandoned
Array ( [id] => 14542 [patent_doc_number] => 07808115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Test circuit under pad' [patent_app_type] => utility [patent_app_number] => 10/990122 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5094 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808115.pdf [firstpage_image] =>[orig_patent_app_number] => 10990122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990122
Test circuit under pad Nov 14, 2004 Issued
Array ( [id] => 4971565 [patent_doc_number] => 20070111567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Method and device for connecting chips' [patent_app_type] => utility [patent_app_number] => 10/577142 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2529 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111567.pdf [firstpage_image] =>[orig_patent_app_number] => 10577142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/577142
Method and device for connecting chips Oct 27, 2004 Issued
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