Search

Tha-o H. Bui

Examiner (ID: 2652, Phone: (571)270-7357 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2824, 2825, 4134
Total Applications
1233
Issued Applications
1026
Pending Applications
100
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18890850 [patent_doc_number] => 11869627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor device comprising memory circuit over control circuits [patent_app_type] => utility [patent_app_number] => 17/606116 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 67 [patent_no_of_words] => 36688 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17606116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/606116
Semiconductor device comprising memory circuit over control circuits May 11, 2020 Issued
Array ( [id] => 17121922 [patent_doc_number] => 11133062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Two memory cells sensed to determine one data value [patent_app_type] => utility [patent_app_number] => 16/869059 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 16080 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869059
Two memory cells sensed to determine one data value May 6, 2020 Issued
Array ( [id] => 17622951 [patent_doc_number] => 11342010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Managing bit line voltage generating circuits in memory devices [patent_app_type] => utility [patent_app_number] => 16/842225 [patent_app_country] => US [patent_app_date] => 2020-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842225
Managing bit line voltage generating circuits in memory devices Apr 6, 2020 Issued
Array ( [id] => 17477080 [patent_doc_number] => 20220084584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => TERNARY MEMORY CELL AND MEMORY DEVICE COMPRISING SAME [patent_app_type] => utility [patent_app_number] => 17/424490 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17424490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/424490
Ternary memory cell and memory device comprising same Apr 2, 2020 Issued
Array ( [id] => 17668120 [patent_doc_number] => 11361823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Semiconductor memory device having bonded first and second semiconductor chips provided with respective impedance calibration control circuits [patent_app_type] => utility [patent_app_number] => 16/831568 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7132 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831568
Semiconductor memory device having bonded first and second semiconductor chips provided with respective impedance calibration control circuits Mar 25, 2020 Issued
Array ( [id] => 16180164 [patent_doc_number] => 20200227133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Memory Repair Scheme [patent_app_type] => utility [patent_app_number] => 16/829149 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829149
Memory repair scheme Mar 24, 2020 Issued
Array ( [id] => 17558901 [patent_doc_number] => 11315620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Semiconductor device performing row hammer refresh operation [patent_app_type] => utility [patent_app_number] => 16/824460 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6106 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824460
Semiconductor device performing row hammer refresh operation Mar 18, 2020 Issued
Array ( [id] => 17002383 [patent_doc_number] => 11081205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Semiconductor apparatus for compensating for degradation and semiconductor system using the same [patent_app_type] => utility [patent_app_number] => 16/819710 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7853 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819710
Semiconductor apparatus for compensating for degradation and semiconductor system using the same Mar 15, 2020 Issued
Array ( [id] => 16162623 [patent_doc_number] => 20200219544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/819451 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819451
Longest element length determination in memory Mar 15, 2020 Issued
Array ( [id] => 17210496 [patent_doc_number] => 11170871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Semiconductor apparatus for compensating for degradation and semiconductor system using the same [patent_app_type] => utility [patent_app_number] => 16/819790 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7852 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819790
Semiconductor apparatus for compensating for degradation and semiconductor system using the same Mar 15, 2020 Issued
Array ( [id] => 17380894 [patent_doc_number] => 11238915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device performing row hammer refresh operation [patent_app_type] => utility [patent_app_number] => 16/818989 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818989
Semiconductor device performing row hammer refresh operation Mar 12, 2020 Issued
Array ( [id] => 17380894 [patent_doc_number] => 11238915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device performing row hammer refresh operation [patent_app_type] => utility [patent_app_number] => 16/818989 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818989
Semiconductor device performing row hammer refresh operation Mar 12, 2020 Issued
Array ( [id] => 17380894 [patent_doc_number] => 11238915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device performing row hammer refresh operation [patent_app_type] => utility [patent_app_number] => 16/818989 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818989
Semiconductor device performing row hammer refresh operation Mar 12, 2020 Issued
Array ( [id] => 17380894 [patent_doc_number] => 11238915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device performing row hammer refresh operation [patent_app_type] => utility [patent_app_number] => 16/818989 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818989
Semiconductor device performing row hammer refresh operation Mar 12, 2020 Issued
Array ( [id] => 16593994 [patent_doc_number] => 10903271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Multilayer back end of line (BEOL)-stackable cross-point memory array with complementary pass transistor selectors [patent_app_type] => utility [patent_app_number] => 16/813721 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 82 [patent_no_of_words] => 12125 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813721
Multilayer back end of line (BEOL)-stackable cross-point memory array with complementary pass transistor selectors Mar 8, 2020 Issued
Array ( [id] => 17978417 [patent_doc_number] => 11495289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Neural network computation circuit including semiconductor memory element, and method of operation [patent_app_type] => utility [patent_app_number] => 16/809365 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6303 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809365
Neural network computation circuit including semiconductor memory element, and method of operation Mar 3, 2020 Issued
Array ( [id] => 16958866 [patent_doc_number] => 11062743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => System and method for providing a configurable timing control for a memory system [patent_app_type] => utility [patent_app_number] => 16/802073 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802073
System and method for providing a configurable timing control for a memory system Feb 25, 2020 Issued
Array ( [id] => 17025198 [patent_doc_number] => 20210249070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Wordline Coupling Techniques [patent_app_type] => utility [patent_app_number] => 16/786779 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786779
Wordline coupling techniques Feb 9, 2020 Issued
Array ( [id] => 16593651 [patent_doc_number] => 10902927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Reducing programming disturbance in memory devices [patent_app_type] => utility [patent_app_number] => 16/784899 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5528 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784899
Reducing programming disturbance in memory devices Feb 6, 2020 Issued
Array ( [id] => 16660382 [patent_doc_number] => 20210057019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH PAGE BUFFERS [patent_app_type] => utility [patent_app_number] => 16/784837 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784837
Semiconductor memory device with cache latches Feb 6, 2020 Issued
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