Search

Tha-o H. Bui

Examiner (ID: 15691, Phone: (571)270-7357 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2824, 2825, 4134
Total Applications
1252
Issued Applications
1043
Pending Applications
102
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20961202 [patent_doc_number] => 12731645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-08 [patent_title] => Semiconductor memory device with reduced write voltage using channel floating and capacitive coupling [patent_app_type] => utility [patent_app_number] => 18/743500 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743500 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743500
SEMICONDUCTOR MEMORY DEVICE Jun 13, 2024 Pending
Array ( [id] => 19726908 [patent_doc_number] => 20250029659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/741633 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741633
THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS Jun 11, 2024 Pending
Array ( [id] => 20324366 [patent_doc_number] => 20250336454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => STATE DEPENDENT VERIFY VOLTAGE RAMPING TIME PERIODS FOR A PROGRAM-VERIFY OPERATION FOR PERFORMANCE GAIN [patent_app_type] => utility [patent_app_number] => 18/740793 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740793
STATE DEPENDENT VERIFY VOLTAGE RAMPING TIME PERIODS FOR A PROGRAM-VERIFY OPERATION FOR PERFORMANCE GAIN Jun 11, 2024 Pending
Array ( [id] => 19696098 [patent_doc_number] => 20250014643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/740905 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740905
MEMORY DEVICE Jun 11, 2024 Pending
Array ( [id] => 19466498 [patent_doc_number] => 20240320168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => STORAGE MEDIUM, STORAGE ELEMENT, STORAGE MEDIUM CONFIGURATION METHOD, AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 18/735729 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735729 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735729
STORAGE MEDIUM, STORAGE ELEMENT, STORAGE MEDIUM CONFIGURATION METHOD, AND DATA TRANSMISSION METHOD Jun 5, 2024 Pending
Array ( [id] => 20305203 [patent_doc_number] => 12451199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor memory device performing program operation and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/679914 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7392 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679914
Semiconductor memory device performing program operation and method of operating the same May 30, 2024 Issued
Array ( [id] => 20396663 [patent_doc_number] => 20250372138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => READ/WRITE CIRCUITS FOR MULTI-STORY CROSS-POINT MEMORY [patent_app_type] => utility [patent_app_number] => 18/679474 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679474
READ/WRITE CIRCUITS FOR MULTI-STORY CROSS-POINT MEMORY May 30, 2024 Pending
Array ( [id] => 20396700 [patent_doc_number] => 20250372175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/677632 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677632
SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES May 28, 2024 Pending
Array ( [id] => 20396678 [patent_doc_number] => 20250372153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => ONE-SIDED TRANSMITTER EQUALIZATION [patent_app_type] => utility [patent_app_number] => 18/677014 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677014
One-sided transmitter equalization May 28, 2024 Issued
Array ( [id] => 20791124 [patent_doc_number] => 12665040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Memory device, memory system, and method of operating the same using bit line bias voltage scheme [patent_app_type] => utility [patent_app_number] => 18/672775 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672775
Memory device, memory system, and method of operating the same using bit line bias voltage scheme May 22, 2024 Issued
Array ( [id] => 20196559 [patent_doc_number] => 20250273269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => PROGRAMMING METHODS FOR MEMORY DEVICES, MEMORY DEVICES AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/671476 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671476
PROGRAMMING METHODS FOR MEMORY DEVICES, MEMORY DEVICES AND MEMORY SYSTEMS May 21, 2024 Pending
Array ( [id] => 19452389 [patent_doc_number] => 20240312519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE TO HOLD 5-BITS OF DATA PER MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/666886 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666886
Semiconductor memory device to hold 5-bits of data per memory cell May 16, 2024 Issued
Array ( [id] => 20063092 [patent_doc_number] => 20250201314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => MEMORY DEVICE AND OPERATION METHOD FOR IMPROVING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/663104 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663104 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663104
MEMORY DEVICE AND OPERATION METHOD FOR IMPROVING A READ OPERATION May 13, 2024 Pending
Array ( [id] => 19589398 [patent_doc_number] => 20240386955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MEMORY DEVICE OF THE PHASE-CHANGE TYPE AND METHOD FOR READING SUCH A DEVICE [patent_app_type] => utility [patent_app_number] => 18/660938 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660938
MEMORY DEVICE OF THE PHASE-CHANGE TYPE AND METHOD FOR READING SUCH A DEVICE May 9, 2024 Pending
Array ( [id] => 20167638 [patent_doc_number] => 20250259685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => HIGH BANDWIDTH NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/660476 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660476
HIGH BANDWIDTH NONVOLATILE MEMORY DEVICES May 9, 2024 Pending
Array ( [id] => 19406886 [patent_doc_number] => 20240290397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => APPARATUS FOR CONTROLLING NAND FLASH MEMORY DEVICE AND METHOD FOR CONTROLLING SAME [patent_app_type] => utility [patent_app_number] => 18/656344 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656344
Apparatus for controlling NAND flash memory device and method for controlling same May 5, 2024 Issued
Array ( [id] => 19531461 [patent_doc_number] => 20240355363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => BIT LINE CONTACT SCHEME IN A MEMORY SYSTEM STACK [patent_app_type] => utility [patent_app_number] => 18/630919 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630919
BIT LINE CONTACT SCHEME IN A MEMORY SYSTEM STACK Apr 8, 2024 Pending
Array ( [id] => 20331859 [patent_doc_number] => 12462137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory card with multiple modes, and host device corresponding to the memory card [patent_app_type] => utility [patent_app_number] => 18/624312 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 11512 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624312
Memory card with multiple modes, and host device corresponding to the memory card Apr 1, 2024 Issued
Array ( [id] => 19305240 [patent_doc_number] => 20240233820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => RRAM CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/615521 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615521
RRAM circuit Mar 24, 2024 Issued
Array ( [id] => 20002529 [patent_doc_number] => 20250140751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH STACKED CHIPS STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/612283 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612283
SEMICONDUCTOR MEMORY DEVICE WITH STACKED CHIPS STRUCTURE Mar 20, 2024 Pending
Menu