Search

Tha-o H. Bui

Examiner (ID: 4699, Phone: (571)270-7357 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825, 4134, 2824
Total Applications
1210
Issued Applications
1019
Pending Applications
94
Abandoned Applications
122

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18143831 [patent_doc_number] => 20230017682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/954664 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954664
Signal sampling circuit and semiconductor memory Sep 27, 2022 Issued
Array ( [id] => 19654255 [patent_doc_number] => 12176055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Data receiving circuit, data receiving system, and memory device [patent_app_type] => utility [patent_app_number] => 17/936107 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 16905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936107
Data receiving circuit, data receiving system, and memory device Sep 27, 2022 Issued
Array ( [id] => 19639508 [patent_doc_number] => 12170121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Semiconductor memory device including command log register and command log output method thereof [patent_app_type] => utility [patent_app_number] => 17/949000 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949000
Semiconductor memory device including command log register and command log output method thereof Sep 19, 2022 Issued
Array ( [id] => 19964639 [patent_doc_number] => 12334154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Write-once memory encoded data [patent_app_type] => utility [patent_app_number] => 17/944692 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3672 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944692
Write-once memory encoded data Sep 13, 2022 Issued
Array ( [id] => 18112659 [patent_doc_number] => 20230005539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS [patent_app_type] => utility [patent_app_number] => 17/943550 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943550
Power off recovery in cross-point memory with threshold switching selectors Sep 12, 2022 Issued
Array ( [id] => 18112668 [patent_doc_number] => 20230005548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => DATA ERASE OPERATIONS FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/943139 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943139
Data erase operations for a memory system Sep 11, 2022 Issued
Array ( [id] => 19781273 [patent_doc_number] => 12230311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Aliased row hammer detector [patent_app_type] => utility [patent_app_number] => 17/941655 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941655
Aliased row hammer detector Sep 8, 2022 Issued
Array ( [id] => 18097044 [patent_doc_number] => 20220415385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Wordline Coupling Techniques [patent_app_type] => utility [patent_app_number] => 17/897716 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897716
Wordline coupling techniques Aug 28, 2022 Issued
Array ( [id] => 19007411 [patent_doc_number] => 20240071482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MIXED BITLINE LOCKOUT FOR QLC/TLC DIE [patent_app_type] => utility [patent_app_number] => 17/895304 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895304
Mixed bitline lockout for QLC/TLC die Aug 24, 2022 Issued
Array ( [id] => 18990870 [patent_doc_number] => 20240062839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/892437 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892437
Performing block-level media management operations for block stripes in a memory device Aug 21, 2022 Issued
Array ( [id] => 19582345 [patent_doc_number] => 12148471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device [patent_app_type] => utility [patent_app_number] => 17/892130 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892130
Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device Aug 21, 2022 Issued
Array ( [id] => 19399491 [patent_doc_number] => 12073876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Memory clock level-shifting buffer with extended range [patent_app_type] => utility [patent_app_number] => 17/891395 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891395
Memory clock level-shifting buffer with extended range Aug 18, 2022 Issued
Array ( [id] => 18990866 [patent_doc_number] => 20240062835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => ADAPTIVE INTEGRITY SCAN RATES IN A MEMORY SUB-SYSTEM BASED ON BLOCK HEALTH METRICS [patent_app_type] => utility [patent_app_number] => 17/891859 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891859
Adaptive integrity scan rates in a memory sub-system based on block health metrics Aug 18, 2022 Issued
Array ( [id] => 19494091 [patent_doc_number] => 12112812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Non-volatile memory with early dummy word line ramp down after precharge [patent_app_type] => utility [patent_app_number] => 17/884929 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 21365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884929
Non-volatile memory with early dummy word line ramp down after precharge Aug 9, 2022 Issued
Array ( [id] => 18158380 [patent_doc_number] => 20230024971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => MEMORY DEVICE, SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/881231 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881231
Memory device with dummy word line, system and method for programming thereof Aug 3, 2022 Issued
Array ( [id] => 19414522 [patent_doc_number] => 12080356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Methods of forming integrated circuit structures for capacitive sense NAND memory [patent_app_type] => utility [patent_app_number] => 17/876718 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 59 [patent_no_of_words] => 22419 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876718
Methods of forming integrated circuit structures for capacitive sense NAND memory Jul 28, 2022 Issued
Array ( [id] => 19523813 [patent_doc_number] => 12125551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Structure for multiple sense amplifiers of memory device [patent_app_type] => utility [patent_app_number] => 17/874973 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 8766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874973
Structure for multiple sense amplifiers of memory device Jul 26, 2022 Issued
Array ( [id] => 19507654 [patent_doc_number] => 12119083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Drive circuit, method for driving drive circuit, and memory [patent_app_type] => utility [patent_app_number] => 17/874813 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8813 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874813
Drive circuit, method for driving drive circuit, and memory Jul 26, 2022 Issued
Array ( [id] => 18143539 [patent_doc_number] => 20230017388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => POWER ARCHITECTURE FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/873850 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873850
Power architecture for non-volatile memory Jul 25, 2022 Issued
Array ( [id] => 19781304 [patent_doc_number] => 12230342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory device, memory system, and read operation method thereof [patent_app_type] => utility [patent_app_number] => 17/871422 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871422
Memory device, memory system, and read operation method thereof Jul 21, 2022 Issued
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