Search

Thao P. Le

Examiner (ID: 9374)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2401
Issued Applications
2209
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17818598 [patent_doc_number] => 11424222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => 3D semiconductor device and structure with metal layers [patent_app_type] => utility [patent_app_number] => 17/680297 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 62 [patent_no_of_words] => 20588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680297
3D semiconductor device and structure with metal layers Feb 24, 2022 Issued
Array ( [id] => 19063207 [patent_doc_number] => 11942459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor device package with exposed bond wires [patent_app_type] => utility [patent_app_number] => 17/670763 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670763
Semiconductor device package with exposed bond wires Feb 13, 2022 Issued
Array ( [id] => 17810949 [patent_doc_number] => 20220262784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => HYBRID ELEMENT AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/667241 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667241
Hybrid element and method of fabricating the same Feb 7, 2022 Issued
Array ( [id] => 19461433 [patent_doc_number] => 12101969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/649910 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/649910
Display device and method of manufacturing the same Feb 2, 2022 Issued
Array ( [id] => 17583210 [patent_doc_number] => 20220140065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT [patent_app_type] => utility [patent_app_number] => 17/578757 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578757
Semiconductor device structure with magnetic element Jan 18, 2022 Issued
Array ( [id] => 17582952 [patent_doc_number] => 20220139807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/577035 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577035
Package and manufacturing method thereof Jan 16, 2022 Issued
Array ( [id] => 18040175 [patent_doc_number] => 20220384392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/648143 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648143
Semiconductor structure and manufacturing method thereof Jan 16, 2022 Issued
Array ( [id] => 17583027 [patent_doc_number] => 20220139882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/575659 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575659
Package structure and method of manufacturing the same Jan 13, 2022 Issued
Array ( [id] => 17583026 [patent_doc_number] => 20220139881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/574953 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574953
Semiconductor package and method of manufacturing the same Jan 12, 2022 Issued
Array ( [id] => 17566593 [patent_doc_number] => 20220130742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION [patent_app_type] => utility [patent_app_number] => 17/566523 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566523
Ground via clustering for crosstalk mitigation Dec 29, 2021 Issued
Array ( [id] => 17551600 [patent_doc_number] => 20220122942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH IMPROVED THERMAL PERFORMANCE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/562290 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562290
Semiconductor device assemblies and systems with improved thermal performance and methods for making the same Dec 26, 2021 Issued
Array ( [id] => 18470808 [patent_doc_number] => 20230205094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SIMULATING DIE ROTATION TO MINIMIZE AREA OVERHEAD OF RETICLE STITCHING FOR STACKED DIES [patent_app_type] => utility [patent_app_number] => 17/561524 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561524
Simulating die rotation to minimize area overhead of reticle stitching for stacked dies Dec 22, 2021 Issued
Array ( [id] => 17536765 [patent_doc_number] => 20220115374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/559826 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559826
Semiconductor device structure Dec 21, 2021 Issued
Array ( [id] => 20204110 [patent_doc_number] => 12406893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Edge-aligned template structure for integrated circuit packages [patent_app_type] => utility [patent_app_number] => 17/557945 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557945
Edge-aligned template structure for integrated circuit packages Dec 20, 2021 Issued
Array ( [id] => 18456272 [patent_doc_number] => 20230197554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => THERMAL BRIDGE INTERPOSER STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/558508 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558508
Thermal bridge interposer structure Dec 20, 2021 Issued
Array ( [id] => 18456424 [patent_doc_number] => 20230197706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTEGRATED DECOUPLING AND ALIGNMENT FEATURES [patent_app_type] => utility [patent_app_number] => 17/555712 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555712
Method for fabricating semiconductor device with integrated decoupling and alignment features Dec 19, 2021 Issued
Array ( [id] => 17660835 [patent_doc_number] => 20220181300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MULTI-TIER BACKSIDE POWER DELIVERY NETWORK FOR DENSE GATE-ON-GATE 3D LOGIC [patent_app_type] => utility [patent_app_number] => 17/541581 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541581 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541581
Multi-tier backside power delivery network for dense gate-on-gate 3D logic Dec 2, 2021 Issued
Array ( [id] => 17933329 [patent_doc_number] => 20220328455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => VERTICAL INTERCONNECT STRUCTURES IN THREE-DIMENSIONAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/538029 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538029
Vertical interconnect structures in three-dimensional integrated circuits Nov 29, 2021 Issued
Array ( [id] => 17886610 [patent_doc_number] => 20220302088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => VERTICAL INTERCONNECT STRUCTURES WITH INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/537026 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537026
Vertical interconnect structures with integrated circuits Nov 28, 2021 Issued
Array ( [id] => 17477484 [patent_doc_number] => 20220084988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/536019 [patent_app_country] => US [patent_app_date] => 2021-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536019
3D semiconductor device and structure with metal layers Nov 26, 2021 Issued
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