
Thao P. Le
Examiner (ID: 3443, Phone: (571)272-1785 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2447 |
| Issued Applications | 2249 |
| Pending Applications | 77 |
| Abandoned Applications | 144 |
Applications
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|---|---|---|---|
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