Search

Thao P. Le

Examiner (ID: 3859, Phone: (571)272-1785 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2417
Issued Applications
2227
Pending Applications
72
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18175175 [patent_doc_number] => 11574892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor package having pads with stepped structure [patent_app_type] => utility [patent_app_number] => 17/216334 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216334 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216334
Semiconductor package having pads with stepped structure Mar 28, 2021 Issued
Array ( [id] => 17630694 [patent_doc_number] => 20220165709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => STACKED SEMICONDUCTOR PACKAGE AND PACKAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/210452 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210452
Stacked semiconductor package and packaging method thereof Mar 22, 2021 Issued
Array ( [id] => 18593349 [patent_doc_number] => 11742260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Three-dimensional device cooling [patent_app_type] => utility [patent_app_number] => 17/207495 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8790 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207495
Three-dimensional device cooling Mar 18, 2021 Issued
Array ( [id] => 19108740 [patent_doc_number] => 11961854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/203759 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7273 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203759
Semiconductor device Mar 16, 2021 Issued
Array ( [id] => 18073725 [patent_doc_number] => 11532565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => System on integrated chips and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/201917 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201917
System on integrated chips and methods of forming the same Mar 14, 2021 Issued
Array ( [id] => 18105570 [patent_doc_number] => 11545468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Wafer stacking method and wafer stacking structure [patent_app_type] => utility [patent_app_number] => 17/202248 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202248
Wafer stacking method and wafer stacking structure Mar 14, 2021 Issued
Array ( [id] => 16959141 [patent_doc_number] => 11063024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Method to form a 3D semiconductor device and structure [patent_app_type] => utility [patent_app_number] => 17/195517 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 62 [patent_no_of_words] => 19710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195517
Method to form a 3D semiconductor device and structure Mar 7, 2021 Issued
Array ( [id] => 18054064 [patent_doc_number] => 11527457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Package structure with buffer layer embedded in lid layer [patent_app_type] => utility [patent_app_number] => 17/185986 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185986
Package structure with buffer layer embedded in lid layer Feb 25, 2021 Issued
Array ( [id] => 17277964 [patent_doc_number] => 20210384162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 17/172478 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172478
Semiconductor chip, semiconductor device, and semiconductor package including the semiconductor chip Feb 9, 2021 Issued
Array ( [id] => 17941746 [patent_doc_number] => 11476205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Package structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/171136 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171136
Package structure and method for forming the same Feb 8, 2021 Issued
Array ( [id] => 18205501 [patent_doc_number] => 11587906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Package structures having underfills [patent_app_type] => utility [patent_app_number] => 17/168238 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168238
Package structures having underfills Feb 4, 2021 Issued
Array ( [id] => 17463821 [patent_doc_number] => 20220077127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/165479 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165479
Semiconductor package including stacked semiconductor chips and method for fabricating the semiconductor package Feb 1, 2021 Issued
Array ( [id] => 18608133 [patent_doc_number] => 11749611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Package with a substrate comprising periphery interconnects [patent_app_type] => utility [patent_app_number] => 17/164723 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10523 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/164723
Package with a substrate comprising periphery interconnects Jan 31, 2021 Issued
Array ( [id] => 17925925 [patent_doc_number] => 11469188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/162444 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162444
Semiconductor package Jan 28, 2021 Issued
Array ( [id] => 16850622 [patent_doc_number] => 20210151367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/248541 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248541
Package including multiple semiconductor devices Jan 27, 2021 Issued
Array ( [id] => 16850622 [patent_doc_number] => 20210151367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/248541 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248541
Package including multiple semiconductor devices Jan 27, 2021 Issued
Array ( [id] => 17971355 [patent_doc_number] => 11488903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor chip package and method of assembly [patent_app_type] => utility [patent_app_number] => 17/160917 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4500 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160917
Semiconductor chip package and method of assembly Jan 27, 2021 Issued
Array ( [id] => 16850622 [patent_doc_number] => 20210151367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/248541 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248541
Package including multiple semiconductor devices Jan 27, 2021 Issued
Array ( [id] => 18263141 [patent_doc_number] => 11610850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Electronic package and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/160749 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3351 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160749
Electronic package and fabrication method thereof Jan 27, 2021 Issued
Array ( [id] => 16850622 [patent_doc_number] => 20210151367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/248541 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248541
Package including multiple semiconductor devices Jan 27, 2021 Issued
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