Search

Thao P. Le

Examiner (ID: 9374)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2401
Issued Applications
2209
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19221562 [patent_doc_number] => 20240186266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR PACKAGE ENABLING REDUCTION IN SEMICONDUCTOR PACKAGE SIZE [patent_app_type] => utility [patent_app_number] => 18/165787 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165787
SEMICONDUCTOR PACKAGE ENABLING REDUCTION IN SEMICONDUCTOR PACKAGE SIZE Feb 6, 2023 Pending
Array ( [id] => 18431715 [patent_doc_number] => 11676945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => 3D semiconductor device and structure with metal layers [patent_app_type] => utility [patent_app_number] => 18/105826 [patent_app_country] => US [patent_app_date] => 2023-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 66 [patent_no_of_words] => 25132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105826
3D semiconductor device and structure with metal layers Feb 3, 2023 Issued
Array ( [id] => 19130953 [patent_doc_number] => 20240136306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/164212 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164212
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Feb 2, 2023 Pending
Array ( [id] => 19130953 [patent_doc_number] => 20240136306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/164212 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164212
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Feb 2, 2023 Pending
Array ( [id] => 18661361 [patent_doc_number] => 20230307375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Semiconductor Package and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/151583 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151583
Semiconductor Package and Method of Forming the Same Jan 8, 2023 Pending
Array ( [id] => 19342685 [patent_doc_number] => 12052892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Display device and method for manufacturing display device [patent_app_type] => utility [patent_app_number] => 18/094861 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094861
Display device and method for manufacturing display device Jan 8, 2023 Issued
Array ( [id] => 18379779 [patent_doc_number] => 20230154868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR DEVICES WITH REINFORCED SUBSTRATES [patent_app_type] => utility [patent_app_number] => 18/151029 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151029
Semiconductor devices with reinforced substrates Jan 5, 2023 Issued
Array ( [id] => 18394883 [patent_doc_number] => 20230163104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR PACKAGE HAVING PADS WITH STEPPED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/092994 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092994
Semiconductor package having pads with stepped structure Jan 3, 2023 Issued
Array ( [id] => 18682429 [patent_doc_number] => 20230320106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/091832 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091832
SEMICONDUCTOR PACKAGE Dec 29, 2022 Issued
Array ( [id] => 18679928 [patent_doc_number] => 20230317586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DIE SUBSTRATE TO OPTIMIZE SIGNAL ROUTING [patent_app_type] => utility [patent_app_number] => 18/090741 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090741
DIE SUBSTRATE TO OPTIMIZE SIGNAL ROUTING Dec 28, 2022 Pending
Array ( [id] => 20216141 [patent_doc_number] => 12412795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Dual down-set conductive terminals for externally mounted passive components [patent_app_type] => utility [patent_app_number] => 18/090273 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090273
Dual down-set conductive terminals for externally mounted passive components Dec 27, 2022 Issued
Array ( [id] => 19285665 [patent_doc_number] => 20240222142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => EFFICIENT AUTOCATALYTIC METALLIZATION OF POLYMERIC SURFACES [patent_app_type] => utility [patent_app_number] => 18/089632 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089632
EFFICIENT AUTOCATALYTIC METALLIZATION OF POLYMERIC SURFACES Dec 27, 2022 Pending
Array ( [id] => 19271565 [patent_doc_number] => 20240215272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/089495 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089495
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF Dec 26, 2022 Pending
Array ( [id] => 19356912 [patent_doc_number] => 12057369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Enhanced base die heat path using through-silicon vias [patent_app_type] => utility [patent_app_number] => 18/088478 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088478
Enhanced base die heat path using through-silicon vias Dec 22, 2022 Issued
Array ( [id] => 20182436 [patent_doc_number] => 20250266394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => DIRECT COOLING FOR SOIC ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/078875 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078875
DIRECT COOLING FOR SOIC ARCHITECTURES Dec 8, 2022 Pending
Array ( [id] => 19679464 [patent_doc_number] => 12191337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Imaging unit, method for manufacturing the same, and electronic apparatus [patent_app_type] => utility [patent_app_number] => 18/060216 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7292 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060216
Imaging unit, method for manufacturing the same, and electronic apparatus Nov 29, 2022 Issued
Array ( [id] => 20360221 [patent_doc_number] => 12476227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Socket to support high performance multi-die ASICs [patent_app_type] => utility [patent_app_number] => 17/993240 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/993240
Socket to support high performance multi-die ASICs Nov 22, 2022 Issued
Array ( [id] => 18252965 [patent_doc_number] => 20230080004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MANUFACTURING A MODULE WITH SOLDER BODY HAVING ELEVATED EDGE [patent_app_type] => utility [patent_app_number] => 17/989196 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989196
Manufacturing a module with solder body having elevated edge Nov 16, 2022 Issued
Array ( [id] => 20132357 [patent_doc_number] => 12374675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method of producing hybrid semiconductor wafer [patent_app_type] => utility [patent_app_number] => 18/055763 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 1188 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055763
Method of producing hybrid semiconductor wafer Nov 14, 2022 Issued
Array ( [id] => 18243208 [patent_doc_number] => 20230075519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/055139 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055139
Package including multiple semiconductor devices Nov 13, 2022 Issued
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