
Thao P. Le
Examiner (ID: 9374)
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2401 |
| Issued Applications | 2209 |
| Pending Applications | 77 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19071196
[patent_doc_number] => 20240105622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE LINE ISOLATION AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/934676
[patent_app_country] => US
[patent_app_date] => 2022-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27939
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934676
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/934676 | Three-dimensional memory device with source line isolation and method of making the same | Sep 22, 2022 | Issued |
Array
(
[id] => 18696452
[patent_doc_number] => 20230326891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/951841
[patent_app_country] => US
[patent_app_date] => 2022-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12987
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951841
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/951841 | Semiconductor memory device | Sep 22, 2022 | Issued |
Array
(
[id] => 20404487
[patent_doc_number] => 12494468
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => 3D system and wafer reconstitution with mid-layer interposer
[patent_app_type] => utility
[patent_app_number] => 17/934409
[patent_app_country] => US
[patent_app_date] => 2022-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 37
[patent_no_of_words] => 2144
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934409
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/934409 | 3D system and wafer reconstitution with mid-layer interposer | Sep 21, 2022 | Issued |
Array
(
[id] => 20063500
[patent_doc_number] => 20250201722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => APPARATUSES AND METHODS FOR BRIDGE-BASED PACKAGING WITH DIRECT POWER DELIVERY
[patent_app_type] => utility
[patent_app_number] => 17/948325
[patent_app_country] => US
[patent_app_date] => 2022-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17948325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/948325 | APPARATUSES AND METHODS FOR BRIDGE-BASED PACKAGING WITH DIRECT POWER DELIVERY | Sep 19, 2022 | Pending |
Array
(
[id] => 18284002
[patent_doc_number] => 20230099474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => RELIABILITY FOR DRAM DEVICE STACK
[patent_app_type] => utility
[patent_app_number] => 17/941792
[patent_app_country] => US
[patent_app_date] => 2022-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8534
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941792
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/941792 | RELIABILITY FOR DRAM DEVICE STACK | Sep 8, 2022 | Pending |
Array
(
[id] => 18166057
[patent_doc_number] => 20230032658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => SEMICONDUCTOR CHIP PACKAGE AND METHOD OF ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 17/940125
[patent_app_country] => US
[patent_app_date] => 2022-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4523
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940125
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/940125 | Semiconductor chip package and method of assembly | Sep 7, 2022 | Issued |
Array
(
[id] => 18097409
[patent_doc_number] => 20220415750
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => THERMOELECTRIC SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
[patent_app_type] => utility
[patent_app_number] => 17/902641
[patent_app_country] => US
[patent_app_date] => 2022-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5054
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902641
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/902641 | Thermoelectric semiconductor device and method of making same | Sep 1, 2022 | Issued |
Array
(
[id] => 18661382
[patent_doc_number] => 20230307396
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => SEMICONDUCTOR DEVICE, WAFER, AND WAFER MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/901448
[patent_app_country] => US
[patent_app_date] => 2022-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901448
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/901448 | Semiconductor device, wafer, and wafer manufacturing method | Aug 31, 2022 | Issued |
Array
(
[id] => 20274888
[patent_doc_number] => 12444673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Electronic package and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/898883
[patent_app_country] => US
[patent_app_date] => 2022-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 1026
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898883
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/898883 | Electronic package and method for manufacturing the same | Aug 29, 2022 | Issued |
Array
(
[id] => 18081155
[patent_doc_number] => 20220406767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULES
[patent_app_type] => utility
[patent_app_number] => 17/822844
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8869
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822844
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/822844 | Power module package for direct cooling multiple power modules | Aug 28, 2022 | Issued |
Array
(
[id] => 18068152
[patent_doc_number] => 20220399240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/893033
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893033
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893033 | Semiconductor package structure and method for manufacturing the same | Aug 21, 2022 | Issued |
Array
(
[id] => 18073759
[patent_doc_number] => 11532599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => 3D semiconductor device and structure with metal layers
[patent_app_type] => utility
[patent_app_number] => 17/882607
[patent_app_country] => US
[patent_app_date] => 2022-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 61
[patent_figures_cnt] => 66
[patent_no_of_words] => 24277
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882607
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/882607 | 3D semiconductor device and structure with metal layers | Aug 7, 2022 | Issued |
Array
(
[id] => 18874757
[patent_doc_number] => 11862580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/874308
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8881
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874308
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874308 | Semiconductor package | Jul 26, 2022 | Issued |
Array
(
[id] => 17993393
[patent_doc_number] => 20220359430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/874030
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7760
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874030
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874030 | Package structure | Jul 25, 2022 | Issued |
Array
(
[id] => 18193758
[patent_doc_number] => 20230047277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => 3D VERTICAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/871855
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871855
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/871855 | 3D VERTICAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | Jul 21, 2022 | Pending |
Array
(
[id] => 18720400
[patent_doc_number] => 11797746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Method of forming semiconductor device having more similar cell densities in alternating rows
[patent_app_type] => utility
[patent_app_number] => 17/865272
[patent_app_country] => US
[patent_app_date] => 2022-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 28
[patent_no_of_words] => 14858
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865272
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/865272 | Method of forming semiconductor device having more similar cell densities in alternating rows | Jul 13, 2022 | Issued |
Array
(
[id] => 18906101
[patent_doc_number] => 20240021586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => STACKED COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) AND METHOD OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 17/812300
[patent_app_country] => US
[patent_app_date] => 2022-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9230
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812300
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/812300 | STACKED COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) AND METHOD OF MANUFACTURE | Jul 12, 2022 | Pending |
Array
(
[id] => 18514694
[patent_doc_number] => 20230230955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-20
[patent_title] => MULTI-CHIP STACKING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/863568
[patent_app_country] => US
[patent_app_date] => 2022-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863568
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/863568 | MULTI-CHIP STACKING METHOD | Jul 12, 2022 | Pending |
Array
(
[id] => 18688514
[patent_doc_number] => 11784260
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/863127
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 31
[patent_no_of_words] => 11176
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863127
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/863127 | Semiconductor devices | Jul 11, 2022 | Issued |
Array
(
[id] => 18883007
[patent_doc_number] => 20240006376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => SEMICONDUCTOR PACKAGES FOR ALTERNATE STACKED MEMORY AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/857062
[patent_app_country] => US
[patent_app_date] => 2022-07-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857062
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/857062 | SEMICONDUCTOR PACKAGES FOR ALTERNATE STACKED MEMORY AND METHODS OF MANUFACTURING THE SAME | Jul 3, 2022 | Pending |