Thao X. Le

Array ( [id] => 519318 [patent_doc_number] => 07193251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'ESD protection cluster and method of providing multi-port ESD protection' [patent_app_type] => utility [patent_app_number] => 10/339192 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2445 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193251.pdf [firstpage_image] =>[orig_patent_app_number] => 10339192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178313 [patent_doc_number] => 06747292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Multi-layer structure for reducing capacitance and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 10/339429 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1715 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747292.pdf [firstpage_image] =>[orig_patent_app_number] => 10339429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1009760 [patent_doc_number] => 06900522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Chamfered semiconductor wafer and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/472518 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3459 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900522.pdf [firstpage_image] =>[orig_patent_app_number] => 10472518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1193749 [patent_doc_number] => 06730959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Structure of flash memory device and fabrication method thereof' [patent_app_type] => B1 [patent_app_number] => 10/065554 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5341 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730959.pdf [firstpage_image] =>[orig_patent_app_number] => 10065554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6778818 [patent_doc_number] => 20030049899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Electrode structures' [patent_app_type] => new [patent_app_number] => 10/242908 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5523 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049899.pdf [firstpage_image] =>[orig_patent_app_number] => 10242908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1241528 [patent_doc_number] => 06683351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Semiconductor device having structures that can avoid deterioration caused by the manufacturing processing' [patent_app_type] => B2 [patent_app_number] => 10/225128 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4819 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683351.pdf [firstpage_image] =>[orig_patent_app_number] => 10225128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6260573 [patent_doc_number] => 20020187603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method for fabricating recessed lightly doped drain field effect transistors' [patent_app_type] => new [patent_app_number] => 10/211543 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2578 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187603.pdf [firstpage_image] =>[orig_patent_app_number] => 10211543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 712180 [patent_doc_number] => 07057230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed' [patent_app_type] => utility [patent_app_number] => 10/484578 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 63 [patent_no_of_words] => 21459 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057230.pdf [firstpage_image] =>[orig_patent_app_number] => 10484578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6692738 [patent_doc_number] => 20030040170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method of reducing the conductivity of a semiconductor and devices made thereby' [patent_app_type] => new [patent_app_number] => 10/200804 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040170.pdf [firstpage_image] =>[orig_patent_app_number] => 10200804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6407246 [patent_doc_number] => 20020182755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Self-aligned MRAM contact and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/196933 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4233 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182755.pdf [firstpage_image] =>[orig_patent_app_number] => 10196933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 397936 [patent_doc_number] => 07294905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Thin film capacitor and electronic circuit component' [patent_app_type] => utility [patent_app_number] => 10/483378 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 10979 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294905.pdf [firstpage_image] =>[orig_patent_app_number] => 10483378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6044323 [patent_doc_number] => 20020167038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Novel high-k dielectric materials and processes for manufacturing them' [patent_app_type] => new [patent_app_number] => 10/190428 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2927 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167038.pdf [firstpage_image] =>[orig_patent_app_number] => 10190428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6535582 [patent_doc_number] => 20020163025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Mixed metal nitride and boride barrier layers' [patent_app_type] => new [patent_app_number] => 10/185009 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5424 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163025.pdf [firstpage_image] =>[orig_patent_app_number] => 10185009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6805105 [patent_doc_number] => 20030232499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Method of making a semiconductor device that includes a dual damascene interconnect' [patent_app_type] => new [patent_app_number] => 10/174804 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232499.pdf [firstpage_image] =>[orig_patent_app_number] => 10174804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6531361 [patent_doc_number] => 20020192979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Dielectric layer forming method and devices formed therewith' [patent_app_type] => new [patent_app_number] => 10/174436 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4970 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192979.pdf [firstpage_image] =>[orig_patent_app_number] => 10174436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6805078 [patent_doc_number] => 20030232472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Methods of fabbricating a stack-gate non-volatile memory device and its contactless memory arrays' [patent_app_type] => new [patent_app_number] => 10/170453 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 641 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232472.pdf [firstpage_image] =>[orig_patent_app_number] => 10170453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5782805 [patent_doc_number] => 20020158283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Fabrication of integrated circuits with borderless vias' [patent_app_type] => new [patent_app_number] => 10/170612 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9475 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158283.pdf [firstpage_image] =>[orig_patent_app_number] => 10170612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6676874 [patent_doc_number] => 20030227014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Process for forming semiconductor layer of micro-and nano-electronic devices' [patent_app_type] => new [patent_app_number] => 10/167683 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4466 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227014.pdf [firstpage_image] =>[orig_patent_app_number] => 10167683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1272652 [patent_doc_number] => 06653659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Silicon carbide inversion channel mosfets' [patent_app_type] => B2 [patent_app_number] => 10/165400 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653659.pdf [firstpage_image] =>[orig_patent_app_number] => 10165400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6701656 [patent_doc_number] => 20030224536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Contact formation' [patent_app_type] => new [patent_app_number] => 10/161863 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224536.pdf [firstpage_image] =>[orig_patent_app_number] => 10161863 [rel_patent_id] =>[rel_patent_doc_number] =>)