Search

Thao X. Le

Supervisory Patent Examiner (ID: 2525, Phone: (571)272-1708 , Office: P/2892 )

Most Active Art Unit
2814
Art Unit(s)
2892, 2814
Total Applications
343
Issued Applications
215
Pending Applications
14
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5933383 [patent_doc_number] => 20020060335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same' [patent_app_type] => new [patent_app_number] => 10/044178 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9522 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060335.pdf [firstpage_image] =>[orig_patent_app_number] => 10044178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044178
Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same Jan 9, 2002 Issued
Array ( [id] => 6854215 [patent_doc_number] => 20030127716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Single layer wiring bond pad with optimum AL film thickness in Cu/FSG process for devices under pads' [patent_app_type] => new [patent_app_number] => 10/043709 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2773 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20030127716.pdf [firstpage_image] =>[orig_patent_app_number] => 10043709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043709
Single layer wiring bond pad with optimum AL film thickness in Cu/FSG process for devices under pads Jan 8, 2002 Abandoned
Array ( [id] => 944300 [patent_doc_number] => 06967354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Light emitting semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/466059 [patent_app_country] => US [patent_app_date] => 2002-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 5249 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967354.pdf [firstpage_image] =>[orig_patent_app_number] => 10466059 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466059
Light emitting semiconductor package Jan 7, 2002 Issued
Array ( [id] => 5968512 [patent_doc_number] => 20020090776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Insulating film formation method, semiconductor device, and production apparatus' [patent_app_type] => new [patent_app_number] => 10/037558 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12354 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090776.pdf [firstpage_image] =>[orig_patent_app_number] => 10037558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037558
Insulating film formation method, semiconductor device, and production apparatus Jan 3, 2002 Issued
Array ( [id] => 6539817 [patent_doc_number] => 20020137310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method and apparatus for fabricating a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/038990 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137310.pdf [firstpage_image] =>[orig_patent_app_number] => 10038990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038990
Method and apparatus for fabricating a semiconductor device Jan 3, 2002 Abandoned
Array ( [id] => 6539984 [patent_doc_number] => 20020137323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Metal ion diffusion barrier layers' [patent_app_type] => new [patent_app_number] => 10/037289 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4461 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137323.pdf [firstpage_image] =>[orig_patent_app_number] => 10037289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037289
Metal ion diffusion barrier layers Jan 2, 2002 Abandoned
Array ( [id] => 1193014 [patent_doc_number] => 06730592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Methods for planarization of metal-containing surfaces using halogens and halide salts' [patent_app_type] => B2 [patent_app_number] => 10/032049 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5520 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730592.pdf [firstpage_image] =>[orig_patent_app_number] => 10032049 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032049
Methods for planarization of metal-containing surfaces using halogens and halide salts Dec 20, 2001 Issued
Array ( [id] => 5856427 [patent_doc_number] => 20020121696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Semiconductor ceramic for thermistors and chip-type thermistor including the same' [patent_app_type] => new [patent_app_number] => 10/017079 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121696.pdf [firstpage_image] =>[orig_patent_app_number] => 10017079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017079
Semiconductor ceramic for thermistors and chip-type thermistor including the same Dec 13, 2001 Issued
Array ( [id] => 1366762 [patent_doc_number] => 06566183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method of making a transistor, in particular spacers of the transistor' [patent_app_type] => B1 [patent_app_number] => 10/017192 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566183.pdf [firstpage_image] =>[orig_patent_app_number] => 10017192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017192
Method of making a transistor, in particular spacers of the transistor Dec 11, 2001 Issued
Array ( [id] => 6696931 [patent_doc_number] => 20030109125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Fuse structure for a semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/013904 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2484 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109125.pdf [firstpage_image] =>[orig_patent_app_number] => 10013904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013904
Fuse structure for a semiconductor device and manufacturing method thereof Dec 9, 2001 Abandoned
Array ( [id] => 6260404 [patent_doc_number] => 20020187566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method for gettering semiconductor device' [patent_app_type] => new [patent_app_number] => 10/005608 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187566.pdf [firstpage_image] =>[orig_patent_app_number] => 10005608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005608
Method for gettering semiconductor device Dec 6, 2001 Abandoned
Array ( [id] => 6696917 [patent_doc_number] => 20030109111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method for forming an ONO structure in one chamber' [patent_app_type] => new [patent_app_number] => 10/002978 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109111.pdf [firstpage_image] =>[orig_patent_app_number] => 10002978 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002978
Method for forming an ONO structure in one chamber Dec 5, 2001 Abandoned
Array ( [id] => 6277187 [patent_doc_number] => 20020106881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Prevention of contact failure by hydrogen treatment' [patent_app_type] => new [patent_app_number] => 10/006578 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1738 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106881.pdf [firstpage_image] =>[orig_patent_app_number] => 10006578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/006578
Prevention of contact failure by hydrogen treatment Dec 5, 2001 Abandoned
Array ( [id] => 1378829 [patent_doc_number] => 06555428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Ferroelectric capacitor and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/001829 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5378 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555428.pdf [firstpage_image] =>[orig_patent_app_number] => 10001829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001829
Ferroelectric capacitor and method for fabricating the same Dec 4, 2001 Issued
Array ( [id] => 7194903 [patent_doc_number] => 20040085704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Integrated circuit with reduced substrate coupling' [patent_app_type] => new [patent_app_number] => 10/450009 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2707 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20040085704.pdf [firstpage_image] =>[orig_patent_app_number] => 10450009 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/450009
Integrated circuit with reduced coupling via the substrate Nov 25, 2001 Issued
Array ( [id] => 6801317 [patent_doc_number] => 20030096482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing' [patent_app_type] => new [patent_app_number] => 10/044220 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2363 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096482.pdf [firstpage_image] =>[orig_patent_app_number] => 10044220 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044220
Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing Nov 19, 2001 Issued
Array ( [id] => 6799532 [patent_doc_number] => 20030094696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'STACKED FILL STRUCTURES FOR SUPPORT OF DIELECTRIC LAYERS' [patent_app_type] => new [patent_app_number] => 09/991769 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5551 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094696.pdf [firstpage_image] =>[orig_patent_app_number] => 09991769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991769
Stacked fill structures for support of dielectric layers Nov 15, 2001 Issued
Array ( [id] => 1249101 [patent_doc_number] => 06674124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Trench MOSFET having low gate charge' [patent_app_type] => B2 [patent_app_number] => 10/002529 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6232 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674124.pdf [firstpage_image] =>[orig_patent_app_number] => 10002529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002529
Trench MOSFET having low gate charge Nov 14, 2001 Issued
Array ( [id] => 6713800 [patent_doc_number] => 20030025148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Structure of a flash memory' [patent_app_type] => new [patent_app_number] => 09/990862 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2317 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025148.pdf [firstpage_image] =>[orig_patent_app_number] => 09990862 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990862
Structure of a flash memory Nov 12, 2001 Abandoned
Array ( [id] => 1273962 [patent_doc_number] => 06649500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/991093 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8328 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649500.pdf [firstpage_image] =>[orig_patent_app_number] => 09991093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991093
Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same Nov 12, 2001 Issued
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