
Thao X. Le
Supervisory Patent Examiner (ID: 2525, Phone: (571)272-1708 , Office: P/2892 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2892, 2814 |
| Total Applications | 343 |
| Issued Applications | 215 |
| Pending Applications | 14 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6630082
[patent_doc_number] => 20020086475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Zero overlap contact/via with metal plug'
[patent_app_type] => new
[patent_app_number] => 10/006639
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20020086475.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006639 | Zero overlap contact/via with metal plug | Nov 7, 2001 | Abandoned |
Array
(
[id] => 1101608
[patent_doc_number] => 06815272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-09
[patent_title] => 'Bottom gate-type thin-film transistor and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 10/008389
[patent_app_country] => US
[patent_app_date] => 2001-11-06
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[pdf_file] => patents/06/815/06815272.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/008389 | Bottom gate-type thin-film transistor and method for manufacturing the same | Nov 5, 2001 | Issued |
Array
(
[id] => 1517386
[patent_doc_number] => 06500764
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Method for thinning a semiconductor substrate'
[patent_app_type] => B1
[patent_app_number] => 10/021547
[patent_app_country] => US
[patent_app_date] => 2001-10-29
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[pdf_file] => patents/06/500/06500764.pdf
[firstpage_image] =>[orig_patent_app_number] => 10021547
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/021547 | Method for thinning a semiconductor substrate | Oct 28, 2001 | Issued |
Array
(
[id] => 6075962
[patent_doc_number] => 20020079514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Metal-oxide-semiconductor transistor structure and method of manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/061140
[patent_app_country] => US
[patent_app_date] => 2001-10-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0079/20020079514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10061140
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/061140 | Metal-oxide-semiconductor transistor structure and method of manufacturing same | Oct 24, 2001 | Abandoned |
Array
(
[id] => 1411907
[patent_doc_number] => 06524902
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[patent_issue_date] => 2003-02-25
[patent_title] => 'Method of manufacturing CMOS semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/001619
[patent_app_country] => US
[patent_app_date] => 2001-10-23
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[pdf_file] => patents/06/524/06524902.pdf
[firstpage_image] =>[orig_patent_app_number] => 10001619
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/001619 | Method of manufacturing CMOS semiconductor device | Oct 22, 2001 | Issued |
Array
(
[id] => 1366795
[patent_doc_number] => 06566185
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[patent_kind] => B2
[patent_issue_date] => 2003-05-20
[patent_title] => 'Method of manufacturing a plural unit high frequency transistor'
[patent_app_type] => B2
[patent_app_number] => 09/973717
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[patent_app_date] => 2001-10-11
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[pdf_file] => patents/06/566/06566185.pdf
[firstpage_image] =>[orig_patent_app_number] => 09973717
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973717 | Method of manufacturing a plural unit high frequency transistor | Oct 10, 2001 | Issued |
Array
(
[id] => 6817896
[patent_doc_number] => 20030068854
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[patent_kind] => A1
[patent_issue_date] => 2003-04-10
[patent_title] => 'Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating Islands'
[patent_app_type] => new
[patent_app_number] => 09/970758
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0068/20030068854.pdf
[firstpage_image] =>[orig_patent_app_number] => 09970758
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/970758 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands | Oct 3, 2001 | Issued |
Array
(
[id] => 6783103
[patent_doc_number] => 20030064550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Method of ion implantation for achieving desired dopant concentration'
[patent_app_type] => new
[patent_app_number] => 09/968388
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0064/20030064550.pdf
[firstpage_image] =>[orig_patent_app_number] => 09968388
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/968388 | Method of ion implantation for achieving desired dopant concentration | Sep 27, 2001 | Abandoned |
Array
(
[id] => 1411919
[patent_doc_number] => 06524903
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[patent_kind] => B2
[patent_issue_date] => 2003-02-25
[patent_title] => 'Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution'
[patent_app_type] => B2
[patent_app_number] => 09/965479
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[patent_app_date] => 2001-09-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/965479 | Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution | Sep 27, 2001 | Issued |
Array
(
[id] => 6781148
[patent_doc_number] => 20030062595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'ONE TIME PROGRAMMABLE FUSE/ANTI-FUSE COMBINATION BASED MEMORY CELL'
[patent_app_type] => new
[patent_app_number] => 09/964768
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[pdf_file] => publications/A1/0062/20030062595.pdf
[firstpage_image] =>[orig_patent_app_number] => 09964768
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964768 | One time programmable fuse/anti-fuse combination based memory cell | Sep 27, 2001 | Issued |
Array
(
[id] => 935635
[patent_doc_number] => 06974985
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-13
[patent_title] => 'Capacitor and method for fabricating the same, and semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 09/960398
[patent_app_country] => US
[patent_app_date] => 2001-09-24
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[pdf_file] => patents/06/974/06974985.pdf
[firstpage_image] =>[orig_patent_app_number] => 09960398
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/960398 | Capacitor and method for fabricating the same, and semiconductor device and method for fabricating the same | Sep 23, 2001 | Issued |
Array
(
[id] => 6692763
[patent_doc_number] => 20030040195
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[patent_issue_date] => 2003-02-27
[patent_title] => 'Method for fabricating low dielectric constant material film'
[patent_app_type] => new
[patent_app_number] => 09/947888
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/947888 | Method for fabricating low dielectric constant material film | Sep 5, 2001 | Abandoned |
Array
(
[id] => 1590730
[patent_doc_number] => 06483137
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[patent_issue_date] => 2002-11-19
[patent_title] => 'Capacitor utilizing c-axis oriented lead germanate film'
[patent_app_type] => B2
[patent_app_number] => 09/942205
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/942205 | Capacitor utilizing c-axis oriented lead germanate film | Aug 28, 2001 | Issued |
Array
(
[id] => 1327432
[patent_doc_number] => 06599846
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[patent_issue_date] => 2003-07-29
[patent_title] => 'Method of forming a silica-containing coating film with a low dielectric constant and semiconductor substrate coated with such a film'
[patent_app_type] => B2
[patent_app_number] => 09/914418
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Array
(
[id] => 6631269
[patent_doc_number] => 20020086541
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[patent_issue_date] => 2002-07-04
[patent_title] => 'Method of forming silicon nitride on a substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/935138 | Method of forming silicon nitride on a substrate | Aug 20, 2001 | Issued |
Array
(
[id] => 6998443
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[patent_kind] => A1
[patent_issue_date] => 2001-12-20
[patent_title] => 'PD-SOI substrate with suppressed floating body effect and method for its fabrication'
[patent_app_type] => new
[patent_app_number] => 09/930451
[patent_app_country] => US
[patent_app_date] => 2001-08-16
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[pdf_file] => publications/A1/0052/20010052621.pdf
[firstpage_image] =>[orig_patent_app_number] => 09930451
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/930451 | PD-SOI substrate with suppressed floating body effect and method for its fabrication | Aug 15, 2001 | Abandoned |
Array
(
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[patent_issue_date] => 2002-12-26
[patent_title] => 'Thin film resistor and manufacturing method thereof'
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Array
(
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Array
(
[id] => 7627905
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[patent_issue_date] => 2004-10-19
[patent_title] => 'Nonvolatile semiconductor device'
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[patent_app_number] => 09/908848
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[firstpage_image] =>[orig_patent_app_number] => 09908848
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/908848 | Nonvolatile semiconductor device | Jul 19, 2001 | Issued |
Array
(
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[patent_title] => 'Semiconductor device and method for manufacturing the same'
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[pdf_file] => publications/A1/0072/20020072184.pdf
[firstpage_image] =>[orig_patent_app_number] => 09910447
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/910447 | Semiconductor device and method for manufacturing the same | Jul 18, 2001 | Abandoned |