
Thao X. Le
Supervisory Patent Examiner (ID: 2525, Phone: (571)272-1708 , Office: P/2892 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2892, 2814 |
| Total Applications | 343 |
| Issued Applications | 215 |
| Pending Applications | 14 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6205380
[patent_doc_number] => 20020070414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Semiconductor component and process for its fabrication'
[patent_app_type] => new
[patent_app_number] => 09/906338
[patent_app_country] => US
[patent_app_date] => 2001-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3748
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20020070414.pdf
[firstpage_image] =>[orig_patent_app_number] => 09906338
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/906338 | Process for fabrication of a semiconductor component having a tungsten oxide layer | Jul 15, 2001 | Issued |
Array
(
[id] => 1171879
[patent_doc_number] => 06753559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-22
[patent_title] => 'Transistor having improved gate structure'
[patent_app_type] => B2
[patent_app_number] => 09/899199
[patent_app_country] => US
[patent_app_date] => 2001-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 4091
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/753/06753559.pdf
[firstpage_image] =>[orig_patent_app_number] => 09899199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/899199 | Transistor having improved gate structure | Jul 5, 2001 | Issued |
Array
(
[id] => 6137866
[patent_doc_number] => 20020000616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Electronic device and a method for making the same'
[patent_app_type] => new
[patent_app_number] => 09/899869
[patent_app_country] => US
[patent_app_date] => 2001-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3770
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000616.pdf
[firstpage_image] =>[orig_patent_app_number] => 09899869
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/899869 | Electronic device and a method for making the same | Jul 4, 2001 | Issued |
Array
(
[id] => 6137974
[patent_doc_number] => 20020000651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 09/897248
[patent_app_country] => US
[patent_app_date] => 2001-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8133
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000651.pdf
[firstpage_image] =>[orig_patent_app_number] => 09897248
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/897248 | Semiconductor device and method of fabricating the same | Jul 1, 2001 | Abandoned |
Array
(
[id] => 1507294
[patent_doc_number] => 06440788
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-08-27
[patent_title] => 'Implant sequence for multi-function semiconductor structure and method'
[patent_app_type] => B2
[patent_app_number] => 09/895159
[patent_app_country] => US
[patent_app_date] => 2001-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 5209
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/440/06440788.pdf
[firstpage_image] =>[orig_patent_app_number] => 09895159
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/895159 | Implant sequence for multi-function semiconductor structure and method | Jul 1, 2001 | Issued |
Array
(
[id] => 6985550
[patent_doc_number] => 20010035543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Confinement of E-fields in high density ferroelectric memory device structures'
[patent_app_type] => new
[patent_app_number] => 09/893155
[patent_app_country] => US
[patent_app_date] => 2001-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4167
[patent_no_of_claims] => 78
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20010035543.pdf
[firstpage_image] =>[orig_patent_app_number] => 09893155
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/893155 | Confinement of E-fields in high density ferroelectric memory device structures | Jun 26, 2001 | Issued |
Array
(
[id] => 6327174
[patent_doc_number] => 20020197765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Organic light emitting devices'
[patent_app_type] => new
[patent_app_number] => 09/887639
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2990
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20020197765.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887639
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887639 | Organic light-emitting devices | Jun 21, 2001 | Issued |
Array
(
[id] => 1297513
[patent_doc_number] => 06627533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-30
[patent_title] => 'Method of manufacturing an insulation film in a semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/880348
[patent_app_country] => US
[patent_app_date] => 2001-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2163
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627533.pdf
[firstpage_image] =>[orig_patent_app_number] => 09880348
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/880348 | Method of manufacturing an insulation film in a semiconductor device | Jun 12, 2001 | Issued |
Array
(
[id] => 6531236
[patent_doc_number] => 20020192974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'Dielectric layer forming method and devices formed therewith'
[patent_app_type] => new
[patent_app_number] => 09/881408
[patent_app_country] => US
[patent_app_date] => 2001-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4976
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0192/20020192974.pdf
[firstpage_image] =>[orig_patent_app_number] => 09881408
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/881408 | Dielectric layer forming method and devices formed therewith | Jun 12, 2001 | Issued |
Array
(
[id] => 6137824
[patent_doc_number] => 20020000608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Vertical MOS transistor and a method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/872798
[patent_app_country] => US
[patent_app_date] => 2001-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3990
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000608.pdf
[firstpage_image] =>[orig_patent_app_number] => 09872798
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/872798 | Vertical MOS transistor and a method of manufacturing the same | May 31, 2001 | Issued |
Array
(
[id] => 6060279
[patent_doc_number] => 20020030203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-14
[patent_title] => 'Buried channel strained silicon FET using a supply layer created through ion implantation'
[patent_app_type] => new
[patent_app_number] => 09/859139
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4259
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20020030203.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859139
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859139 | Buried channel strained silicon FET using a supply layer created through ion implantation | May 15, 2001 | Issued |
Array
(
[id] => 6048162
[patent_doc_number] => 20020168823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Method for fabricating recessed lightly doped drain field effect transistors'
[patent_app_type] => new
[patent_app_number] => 09/850096
[patent_app_country] => US
[patent_app_date] => 2001-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1918
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20020168823.pdf
[firstpage_image] =>[orig_patent_app_number] => 09850096
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/850096 | Method for fabricating recessed lightly doped drain field effect transistors | May 7, 2001 | Abandoned |
Array
(
[id] => 6044431
[patent_doc_number] => 20020167086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Barrier structures for integration of high K oxides with Cu and AI electrodes'
[patent_app_type] => new
[patent_app_number] => 09/681609
[patent_app_country] => US
[patent_app_date] => 2001-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4400
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20020167086.pdf
[firstpage_image] =>[orig_patent_app_number] => 09681609
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/681609 | Barrier structures for integration of high K oxides with Cu and Al electrodes | May 7, 2001 | Issued |
Array
(
[id] => 5905359
[patent_doc_number] => 20020142144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Single c-axis PGO thin film electrodes having good surface smoothness and uniformity and methods for making the same'
[patent_app_type] => new
[patent_app_number] => 09/820078
[patent_app_country] => US
[patent_app_date] => 2001-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2417
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20020142144.pdf
[firstpage_image] =>[orig_patent_app_number] => 09820078
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/820078 | Single c-axis PGO thin film electrodes having good surface smoothness and uniformity and methods for making the same | Mar 27, 2001 | Issued |
Array
(
[id] => 1214158
[patent_doc_number] => 06710388
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor'
[patent_app_type] => B2
[patent_app_number] => 09/801209
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4672
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/710/06710388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801209 | Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor | Mar 6, 2001 | Issued |
Array
(
[id] => 956498
[patent_doc_number] => 06956250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'Gallium nitride materials including thermally conductive regions'
[patent_app_type] => utility
[patent_app_number] => 09/792409
[patent_app_country] => US
[patent_app_date] => 2001-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 5391
[patent_no_of_claims] => 74
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/956/06956250.pdf
[firstpage_image] =>[orig_patent_app_number] => 09792409
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/792409 | Gallium nitride materials including thermally conductive regions | Feb 22, 2001 | Issued |
Array
(
[id] => 6891253
[patent_doc_number] => 20010017415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 09/779565
[patent_app_country] => US
[patent_app_date] => 2001-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4865
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20010017415.pdf
[firstpage_image] =>[orig_patent_app_number] => 09779565
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/779565 | Semiconductor device and manufacturing method thereof | Feb 8, 2001 | Abandoned |
Array
(
[id] => 941482
[patent_doc_number] => 06969873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-29
[patent_title] => 'Nitride gallium compound semiconductor light emission device'
[patent_app_type] => utility
[patent_app_number] => 09/775838
[patent_app_country] => US
[patent_app_date] => 2001-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 6788
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/969/06969873.pdf
[firstpage_image] =>[orig_patent_app_number] => 09775838
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775838 | Nitride gallium compound semiconductor light emission device | Jan 31, 2001 | Issued |
Array
(
[id] => 1272682
[patent_doc_number] => 06653666
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-25
[patent_title] => 'J-FET semiconductor configuration'
[patent_app_type] => B2
[patent_app_number] => 09/767419
[patent_app_country] => US
[patent_app_date] => 2001-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3693
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/653/06653666.pdf
[firstpage_image] =>[orig_patent_app_number] => 09767419
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/767419 | J-FET semiconductor configuration | Jan 22, 2001 | Issued |
Array
(
[id] => 1361385
[patent_doc_number] => 06569718
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-27
[patent_title] => 'Top gate thin-film transistor and method of producing the same'
[patent_app_type] => B2
[patent_app_number] => 09/754180
[patent_app_country] => US
[patent_app_date] => 2001-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4600
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/569/06569718.pdf
[firstpage_image] =>[orig_patent_app_number] => 09754180
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/754180 | Top gate thin-film transistor and method of producing the same | Jan 2, 2001 | Issued |