Search

Theodore C. Parsons

Examiner (ID: 12791, Phone: (571)270-1475 , Office: P/2494 )

Most Active Art Unit
2494
Art Unit(s)
2494
Total Applications
531
Issued Applications
401
Pending Applications
57
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8386671 [patent_doc_number] => 08264072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Electronic device' [patent_app_type] => utility [patent_app_number] => 11/876271 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4119 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11876271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876271
Electronic device Oct 21, 2007 Issued
Array ( [id] => 4963154 [patent_doc_number] => 20080105974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'PACKAGE STRUCTURE AND PACKAGE SUBSTRATE THEREOF' [patent_app_type] => utility [patent_app_number] => 11/870251 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105974.pdf [firstpage_image] =>[orig_patent_app_number] => 11870251 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/870251
Package structure and package substrate thereof Oct 9, 2007 Issued
Array ( [id] => 6611382 [patent_doc_number] => 20100002896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Hearing Aid Having an Occlusion Reduction Unit and Method for Occlusion Reduction' [patent_app_type] => utility [patent_app_number] => 12/311629 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7238 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002896.pdf [firstpage_image] =>[orig_patent_app_number] => 12311629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/311629
Hearing aid having an occlusion reduction unit and method for occlusion reduction Oct 9, 2007 Issued
Array ( [id] => 5346182 [patent_doc_number] => 20090001543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/869052 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001543.pdf [firstpage_image] =>[orig_patent_app_number] => 11869052 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869052
Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same Oct 8, 2007 Issued
Array ( [id] => 5439356 [patent_doc_number] => 20090090995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'On-chip inductors with through-silicon-via fence for Q improvement' [patent_app_type] => utility [patent_app_number] => 11/868392 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20090090995.pdf [firstpage_image] =>[orig_patent_app_number] => 11868392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868392
On-chip inductors with through-silicon-via fence for Q improvement Oct 4, 2007 Issued
Array ( [id] => 5319880 [patent_doc_number] => 20090057870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'STACKED SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME' [patent_app_type] => utility [patent_app_number] => 11/868041 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3265 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057870.pdf [firstpage_image] =>[orig_patent_app_number] => 11868041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868041
STACKED SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME Oct 4, 2007 Abandoned
Array ( [id] => 7967913 [patent_doc_number] => 07939939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Stable gold bump solder connections' [patent_app_type] => utility [patent_app_number] => 11/867051 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939939.pdf [firstpage_image] =>[orig_patent_app_number] => 11867051 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867051
Stable gold bump solder connections Oct 3, 2007 Issued
Array ( [id] => 5439386 [patent_doc_number] => 20090091025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'METHOD FOR FORMING AND RELEASING INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 11/867652 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5414 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091025.pdf [firstpage_image] =>[orig_patent_app_number] => 11867652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867652
METHOD FOR FORMING AND RELEASING INTERCONNECTS Oct 3, 2007 Abandoned
Array ( [id] => 7967913 [patent_doc_number] => 07939939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Stable gold bump solder connections' [patent_app_type] => utility [patent_app_number] => 11/867051 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939939.pdf [firstpage_image] =>[orig_patent_app_number] => 11867051 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867051
Stable gold bump solder connections Oct 3, 2007 Issued
Array ( [id] => 4691214 [patent_doc_number] => 20080083984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Wiring board' [patent_app_type] => utility [patent_app_number] => 11/905721 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083984.pdf [firstpage_image] =>[orig_patent_app_number] => 11905721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905721
Wiring board Oct 2, 2007 Abandoned
Array ( [id] => 4941819 [patent_doc_number] => 20080079142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Wafer-level MEMS package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/906551 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6152 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20080079142.pdf [firstpage_image] =>[orig_patent_app_number] => 11906551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906551
Wafer-level MEMS package and manufacturing method thereof Oct 1, 2007 Abandoned
Array ( [id] => 5425897 [patent_doc_number] => 20090085207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Ball grid array substrate package and solder pad' [patent_app_type] => utility [patent_app_number] => 11/904841 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2759 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085207.pdf [firstpage_image] =>[orig_patent_app_number] => 11904841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904841
Ball grid array substrate package and solder pad Sep 27, 2007 Abandoned
Array ( [id] => 9167304 [patent_doc_number] => 08592987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor element comprising a supporting structure and production method' [patent_app_type] => utility [patent_app_number] => 11/862211 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3300 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11862211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862211
Semiconductor element comprising a supporting structure and production method Sep 26, 2007 Issued
Array ( [id] => 5288147 [patent_doc_number] => 20090020877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'TRANSMISSION LINE STRUCTURE AND SIGNAL TRANSMISSION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/860771 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20090020877.pdf [firstpage_image] =>[orig_patent_app_number] => 11860771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860771
TRANSMISSION LINE STRUCTURE AND SIGNAL TRANSMISSION STRUCTURE Sep 24, 2007 Abandoned
Array ( [id] => 7530781 [patent_doc_number] => 07843004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Power MOSFET with recessed field plate' [patent_app_type] => utility [patent_app_number] => 11/903972 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 43 [patent_no_of_words] => 6428 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843004.pdf [firstpage_image] =>[orig_patent_app_number] => 11903972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/903972
Power MOSFET with recessed field plate Sep 24, 2007 Issued
Array ( [id] => 8760674 [patent_doc_number] => 08421198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Integrated circuit package system with external interconnects at high density' [patent_app_type] => utility [patent_app_number] => 11/856841 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4310 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11856841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856841
Integrated circuit package system with external interconnects at high density Sep 17, 2007 Issued
Array ( [id] => 10016062 [patent_doc_number] => 09059083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/855712 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7907 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11855712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855712
Semiconductor device Sep 13, 2007 Issued
Array ( [id] => 5449895 [patent_doc_number] => 20090065931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF' [patent_app_type] => utility [patent_app_number] => 11/853461 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1934 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065931.pdf [firstpage_image] =>[orig_patent_app_number] => 11853461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853461
PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF Sep 10, 2007 Abandoned
Array ( [id] => 7519296 [patent_doc_number] => 07973399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Embedded chip package' [patent_app_type] => utility [patent_app_number] => 11/849371 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 7905 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/973/07973399.pdf [firstpage_image] =>[orig_patent_app_number] => 11849371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849371
Embedded chip package Sep 3, 2007 Issued
Array ( [id] => 8578293 [patent_doc_number] => 08344505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Wafer level packaging of semiconductor chips' [patent_app_type] => utility [patent_app_number] => 11/847101 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11847101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847101
Wafer level packaging of semiconductor chips Aug 28, 2007 Issued
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