Theresa T. Doan

Array ( [id] => 15823225 [patent_doc_number] => 10636809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/126259 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14753203 [patent_doc_number] => 20190259775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/126209 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13581777 [patent_doc_number] => 20180342437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => CHIP ON FILM PACKAGE AND HEAT-DISSIPATION STRUCTURE FOR A CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 16/055183 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16293637 [patent_doc_number] => 10770492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Chip scale package and related methods [patent_app_type] => utility [patent_app_number] => 16/054067 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 2945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13598085 [patent_doc_number] => 20180350591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Lattice-Mismatched Semiconductor Substrates with Defect Reduction [patent_app_type] => utility [patent_app_number] => 16/045618 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13559291 [patent_doc_number] => 20180331193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/044581 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15200419 [patent_doc_number] => 10497712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 16/041577 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 41 [patent_no_of_words] => 16996 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13581913 [patent_doc_number] => 20180342505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 16/037581 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16202008 [patent_doc_number] => 10727188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die [patent_app_type] => utility [patent_app_number] => 16/035838 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 3367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14955511 [patent_doc_number] => 10439035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Schottky contact structure for semiconductor devices and method for forming such Schottky contact structure [patent_app_type] => utility [patent_app_number] => 16/033500 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3317 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13514547 [patent_doc_number] => 20180308816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING [patent_app_type] => utility [patent_app_number] => 16/025126 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13543493 [patent_doc_number] => 20180323293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/023418 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15611699 [patent_doc_number] => 10586921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Forming self-aligned contacts on pillar structures [patent_app_type] => utility [patent_app_number] => 16/021214 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4993 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15332325 [patent_doc_number] => 20200006492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING GERMANIUM-BASED CHANNELS [patent_app_type] => utility [patent_app_number] => 16/022510 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15611697 [patent_doc_number] => 10586920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Forming self-aligned contacts on pillar structures [patent_app_type] => utility [patent_app_number] => 16/021195 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13499837 [patent_doc_number] => 20180301461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/012285 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16210686 [patent_doc_number] => 20200243676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ELECTRICAL COUPLING STRUCTURE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/635617 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16635617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15841289 [patent_doc_number] => 20200135927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => FINFET WITH IMPROVED NITRIDE TO FIN SPACING [patent_app_type] => utility [patent_app_number] => 16/006377 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15259967 [patent_doc_number] => 20190378717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => INTEGRATION OF DEVICE REGIONS [patent_app_type] => utility [patent_app_number] => 16/003902 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15611481 [patent_doc_number] => 10586810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => SOI substrate compatible with the RFSOI and FDSOI technologies [patent_app_type] => utility [patent_app_number] => 16/003199 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6031 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003199 [rel_patent_id] =>[rel_patent_doc_number] =>)