Search

Theresa T. Doan

Examiner (ID: 9173)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1974
Issued Applications
1714
Pending Applications
87
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14317103 [patent_doc_number] => 20190148255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/884397 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884397
Semicondcutor package and manufacturing method thereof Jan 30, 2018 Issued
Array ( [id] => 12779704 [patent_doc_number] => 20180151736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => Methods of Fabricating Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 15/877563 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/877563
Methods of fabricating semiconductor devices Jan 22, 2018 Issued
Array ( [id] => 12716770 [patent_doc_number] => 20180130756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/867080 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867080
Semiconductor device structure Jan 9, 2018 Issued
Array ( [id] => 12738856 [patent_doc_number] => 20180138119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => DIELECTRIC THERMAL CONDUCTOR FOR PASSIVATING EFUSE AND METAL RESISTOR [patent_app_type] => utility [patent_app_number] => 15/850564 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850564
Dielectric thermal conductor for passivating eFuse and metal resistor Dec 20, 2017 Issued
Array ( [id] => 14920513 [patent_doc_number] => 10431584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor device including fin structures and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/839286 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839286
Semiconductor device including fin structures and manufacturing method thereof Dec 11, 2017 Issued
Array ( [id] => 12631818 [patent_doc_number] => 20180102436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => SEMICONDUCTOR FIN FET DEVICE WITH EPITAXIAL SOURCE/DRAIN [patent_app_type] => utility [patent_app_number] => 15/837826 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837826
Semiconductor Fin FET device with epitaxial source/drain Dec 10, 2017 Issued
Array ( [id] => 12624105 [patent_doc_number] => 20180099865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => SEMICONDUCTOR MEMS STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/819346 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819346 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819346
Semiconductor MEMS structure Nov 20, 2017 Issued
Array ( [id] => 15556345 [patent_doc_number] => 20200062584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => DAMPING SYSTEM FOR A MOBILE MASS OF A MEMS DEVICE [patent_app_type] => utility [patent_app_number] => 16/462613 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/462613
Damping system for a mobile mass of a MEMS device Nov 19, 2017 Issued
Array ( [id] => 15625785 [patent_doc_number] => 20200083297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SOLID-STATE IMAGE PICKUP ELEMENT AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/462683 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/462683
Solid-state image pickup element and manufacturing method thereof, and electronic device Nov 16, 2017 Issued
Array ( [id] => 14125353 [patent_doc_number] => 10249540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Dual channel CMOS having common gate stacks [patent_app_type] => utility [patent_app_number] => 15/813958 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6587 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813958
Dual channel CMOS having common gate stacks Nov 14, 2017 Issued
Array ( [id] => 12236084 [patent_doc_number] => 20180068946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'ISOLATION DEVICE' [patent_app_type] => utility [patent_app_number] => 15/798963 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 20495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798963
Isolation device Oct 30, 2017 Issued
Array ( [id] => 14429809 [patent_doc_number] => 10319718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Discrete capacitor and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/784985 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 66 [patent_no_of_words] => 34371 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784985
Discrete capacitor and manufacturing method thereof Oct 15, 2017 Issued
Array ( [id] => 13006167 [patent_doc_number] => 10026758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Array substrate, manufacturing method thereof, display panel, and display device [patent_app_type] => utility [patent_app_number] => 15/782240 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4432 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782240 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782240
Array substrate, manufacturing method thereof, display panel, and display device Oct 11, 2017 Issued
Array ( [id] => 14397691 [patent_doc_number] => 10312136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Etch damage and ESL free dual damascene metal interconnect [patent_app_type] => utility [patent_app_number] => 15/726590 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726590
Etch damage and ESL free dual damascene metal interconnect Oct 5, 2017 Issued
Array ( [id] => 14301091 [patent_doc_number] => 10290678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Magnetic shielding package structure for MRAM device and method for producing the same [patent_app_type] => utility [patent_app_number] => 15/716115 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2834 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716115
Magnetic shielding package structure for MRAM device and method for producing the same Sep 25, 2017 Issued
Array ( [id] => 12263827 [patent_doc_number] => 20180083023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/706206 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706206
Semiconductor memory and semiconductor memory manufacturing method Sep 14, 2017 Issued
Array ( [id] => 12141081 [patent_doc_number] => 20180019164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/705426 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705426
Method for forming improved liner layer and semiconductor device including the same Sep 14, 2017 Issued
Array ( [id] => 14079225 [patent_doc_number] => 20190088500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => INTERCONNECTS FORMED BY A METAL REPLACEMENT PROCESS [patent_app_type] => utility [patent_app_number] => 15/705956 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705956
Interconnects formed by a metal replacement process Sep 14, 2017 Issued
Array ( [id] => 12759898 [patent_doc_number] => 20180145134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/706554 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 622 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706554
Semiconductor device Sep 14, 2017 Issued
Array ( [id] => 14079467 [patent_doc_number] => 20190088621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Semiconductor Device and Method of Forming Embedded Die Substrate, and System-in-Package Modules with the Same [patent_app_type] => utility [patent_app_number] => 15/706584 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706584
Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same Sep 14, 2017 Issued
Menu