Search

Theresa T. Doan

Examiner (ID: 9173)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1974
Issued Applications
1714
Pending Applications
87
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13257449 [patent_doc_number] => 10141422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Method of manufacturing a semiconductor device integrating a vertical conduction transistor, and semiconductor device [patent_app_type] => utility [patent_app_number] => 15/595256 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3566 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/595256
Method of manufacturing a semiconductor device integrating a vertical conduction transistor, and semiconductor device May 14, 2017 Issued
Array ( [id] => 13293635 [patent_doc_number] => 10158018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/590210 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 4935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590210
Semiconductor device and manufacturing method thereof May 8, 2017 Issued
Array ( [id] => 14094303 [patent_doc_number] => 10243066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Producing a semiconductor device by epitaxial growth [patent_app_type] => utility [patent_app_number] => 15/589352 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589352
Producing a semiconductor device by epitaxial growth May 7, 2017 Issued
Array ( [id] => 13283493 [patent_doc_number] => 10153338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method of manufacturing a capacitor [patent_app_type] => utility [patent_app_number] => 15/497594 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497594
Method of manufacturing a capacitor Apr 25, 2017 Issued
Array ( [id] => 16249490 [patent_doc_number] => 10748865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Copper paste for joining, method for manufacturing joined body, and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/096807 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 21065 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16096807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/096807
Copper paste for joining, method for manufacturing joined body, and method for manufacturing semiconductor device Apr 19, 2017 Issued
Array ( [id] => 12026916 [patent_doc_number] => 20170317015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/484714 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6449 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484714
Power module package having patterned insulation metal substrate Apr 10, 2017 Issued
Array ( [id] => 13019117 [patent_doc_number] => 10032675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Method for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/473614 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3992 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473614
Method for fabricating semiconductor device Mar 29, 2017 Issued
Array ( [id] => 13660979 [patent_doc_number] => 10160641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Simplified MEMS device fabrication process [patent_app_type] => utility [patent_app_number] => 15/468682 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 37 [patent_no_of_words] => 9489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468682
Simplified MEMS device fabrication process Mar 23, 2017 Issued
Array ( [id] => 13419917 [patent_doc_number] => 20180261501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/453505 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453505
Structure and formation method of interconnection structure of semiconductor device structure Mar 7, 2017 Issued
Array ( [id] => 13420123 [patent_doc_number] => 20180261604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => ACTIVE CONTACT AND GATE CONTACT INTERCONNECT FOR MITIGATING ADJACENT GATE ELECTRODE SHORTAGES [patent_app_type] => utility [patent_app_number] => 15/453124 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453124 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453124
Active contact and gate contact interconnect for mitigating adjacent gate electrode shortages Mar 7, 2017 Issued
Array ( [id] => 12595878 [patent_doc_number] => 20180090456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/453471 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453471
Semiconductor device Mar 7, 2017 Issued
Array ( [id] => 13420013 [patent_doc_number] => 20180261549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 15/452888 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452888
Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die Mar 7, 2017 Issued
Array ( [id] => 13420265 [patent_doc_number] => 20180261675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/453351 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453351
Semiconductor structure and manufacturing method thereof Mar 7, 2017 Issued
Array ( [id] => 11990317 [patent_doc_number] => 20170294472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'PHOTOELECTRIC CONVERSION DEVICE, MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION DEVICE, AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/452988 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6892 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452988
Photoelectric conversion device, manufacturing method of photoelectric conversion device, and imaging system Mar 7, 2017 Issued
Array ( [id] => 13201675 [patent_doc_number] => 10115758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Isolation structure for reducing crosstalk between pixels and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/452935 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 5947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452935
Isolation structure for reducing crosstalk between pixels and fabrication method thereof Mar 7, 2017 Issued
Array ( [id] => 12027099 [patent_doc_number] => 20170317198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/452780 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6024 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452780
Method for manufacturing a bipolar junction transistor Mar 7, 2017 Issued
Array ( [id] => 12257031 [patent_doc_number] => 09929182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Semiconductor structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 15/452788 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5584 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452788
Semiconductor structure and fabrication method thereof Mar 7, 2017 Issued
Array ( [id] => 13006297 [patent_doc_number] => 10026823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Schottky contact structure for semiconductor devices and method for forming such schottky contact structure [patent_app_type] => utility [patent_app_number] => 15/452986 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3288 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452986 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452986
Schottky contact structure for semiconductor devices and method for forming such schottky contact structure Mar 7, 2017 Issued
Array ( [id] => 13188295 [patent_doc_number] => 10109675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Forming self-aligned contacts on pillar structures [patent_app_type] => utility [patent_app_number] => 15/453432 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4994 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453432
Forming self-aligned contacts on pillar structures Mar 7, 2017 Issued
Array ( [id] => 12250316 [patent_doc_number] => 09923100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Flash memory structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 15/452836 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7406 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452836 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452836
Flash memory structure and fabrication method thereof Mar 7, 2017 Issued
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