Theresa T. Doan

Array ( [id] => 11346270 [patent_doc_number] => 09530686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'MOS transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/043830 [patent_app_country] => US [patent_app_date] => 2016-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2731 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802687 [patent_doc_number] => 20160148844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'MOS Transistor Structure and Method' [patent_app_type] => utility [patent_app_number] => 15/009942 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11489392 [patent_doc_number] => 09595465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Vias and methods of formation thereof' [patent_app_type] => utility [patent_app_number] => 15/009364 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 5502 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475677 [patent_doc_number] => 20170062460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/008579 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11861952 [patent_doc_number] => 09741641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Method for manufacturing semiconductor device, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/997509 [patent_app_country] => US [patent_app_date] => 2016-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 15361 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11163683 [patent_doc_number] => 09397199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-19 [patent_title] => 'Methods of forming multi-Vt III-V TFET devices' [patent_app_type] => utility [patent_app_number] => 14/992209 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 48 [patent_no_of_words] => 1782 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13499725 [patent_doc_number] => 20180301405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => CONDUCTIVE BASE EMBEDDED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 15/776402 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15776402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13653589 [patent_doc_number] => 09853116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Partial sacrificial dummy gate with CMOS device with high-k metal gate [patent_app_type] => utility [patent_app_number] => 14/968471 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 3518 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11259531 [patent_doc_number] => 09484436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/954635 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 11865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11227585 [patent_doc_number] => 09455312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Multiple depth vias in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/949274 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3427 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11233829 [patent_doc_number] => 09461064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Multi-layer memory array and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 14/948482 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 42 [patent_no_of_words] => 4730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10753090 [patent_doc_number] => 20160099242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'SEMICONDUCTOR DEVICE EMPLOYING TRENCHES FOR ACTIVE GATE AND ISOLATION' [patent_app_type] => utility [patent_app_number] => 14/880982 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6292 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11544781 [patent_doc_number] => 20170098606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'SEMICONDUCTOR STRUCTURE WITH ULTRA THICK METAL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/874147 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14874147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11524613 [patent_doc_number] => 09608024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'CMOS image sensor for reducing dead zone' [patent_app_type] => utility [patent_app_number] => 14/872691 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6642 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10772187 [patent_doc_number] => 20160118343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/872275 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12412 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11180809 [patent_doc_number] => 09412807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Semiconductor structure' [patent_app_type] => utility [patent_app_number] => 14/872791 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11539468 [patent_doc_number] => 09613884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/872868 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10753059 [patent_doc_number] => 20160099211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'SYSTEM ON CHIP' [patent_app_type] => utility [patent_app_number] => 14/872774 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8935 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10795265 [patent_doc_number] => 20160141423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'Contacts For Highly Scaled Transistors' [patent_app_type] => utility [patent_app_number] => 14/872673 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11180788 [patent_doc_number] => 09412786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Magnetoresistive device design and process integration with surrounding circuitry' [patent_app_type] => utility [patent_app_number] => 14/872708 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872708 [rel_patent_id] =>[rel_patent_doc_number] =>)