Search

Theresa T. Doan

Examiner (ID: 9173)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1974
Issued Applications
1714
Pending Applications
87
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10125319 [patent_doc_number] => 09159685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Conductive structure and method for forming the same' [patent_app_type] => utility [patent_app_number] => 14/494026 [patent_app_country] => US [patent_app_date] => 2014-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3063 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/494026
Conductive structure and method for forming the same Sep 22, 2014 Issued
Array ( [id] => 9796616 [patent_doc_number] => 20150008560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR LOW RESISTIVE THIN FILM RESISTOR INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 14/492331 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3996 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492331
Semiconductor device and method for low resistive thin film resistor interconnect Sep 21, 2014 Issued
Array ( [id] => 9861837 [patent_doc_number] => 20150041854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'FinFET Low Resistivity Contact Formation Method' [patent_app_type] => utility [patent_app_number] => 14/491848 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/491848
FinFET low resistivity contact formation method Sep 18, 2014 Issued
Array ( [id] => 10638609 [patent_doc_number] => 09356121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Divot-free planarization dielectric layer for replacement gate' [patent_app_type] => utility [patent_app_number] => 14/486128 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6066 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486128 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486128
Divot-free planarization dielectric layer for replacement gate Sep 14, 2014 Issued
Array ( [id] => 10974892 [patent_doc_number] => 20140377927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE' [patent_app_type] => utility [patent_app_number] => 14/481178 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9673 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481178
Self-aligned contact structure for replacement metal gate Sep 8, 2014 Issued
Array ( [id] => 10964824 [patent_doc_number] => 20140367856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'SEMICONDUCTOR MANUFACTURING PROCESS AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/474558 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2402 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14474558 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/474558
SEMICONDUCTOR MANUFACTURING PROCESS AND STRUCTURE THEREOF Sep 1, 2014 Abandoned
Array ( [id] => 11802443 [patent_doc_number] => 09543348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Backlight image sensor chip having improved chip driving performance' [patent_app_type] => utility [patent_app_number] => 14/912373 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3148 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14912373 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/912373
Backlight image sensor chip having improved chip driving performance Aug 11, 2014 Issued
Array ( [id] => 10916588 [patent_doc_number] => 20140319607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MOS WITH RECESSED LIGHTLY-DOPED DRAIN' [patent_app_type] => utility [patent_app_number] => 14/326893 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326893 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326893
MOS with recessed lightly-doped drain Jul 8, 2014 Issued
Array ( [id] => 10544759 [patent_doc_number] => 09269897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Device structure for a RRAM and method' [patent_app_type] => utility [patent_app_number] => 14/310113 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6344 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310113
Device structure for a RRAM and method Jun 19, 2014 Issued
Array ( [id] => 10158752 [patent_doc_number] => 09190536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Junction field effect transistor' [patent_app_type] => utility [patent_app_number] => 14/296497 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296497
Junction field effect transistor Jun 4, 2014 Issued
Array ( [id] => 10252343 [patent_doc_number] => 20150137339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/296061 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2891 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296061
Semiconductor package and method of manufacturing the same Jun 3, 2014 Issued
Array ( [id] => 11214778 [patent_doc_number] => 09443818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Power semiconductor module' [patent_app_type] => utility [patent_app_number] => 14/296094 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4170 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296094
Power semiconductor module Jun 3, 2014 Issued
Array ( [id] => 10472324 [patent_doc_number] => 20150357340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Method for filling polysilicon gate in semiconductor devices, and semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/296226 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5302 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296226 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296226
Method for filling polysilicon gate in semiconductor devices, and semiconductor devices Jun 3, 2014 Issued
Array ( [id] => 10563815 [patent_doc_number] => 09287497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Integrated circuits with hall effect sensors and methods for producing such integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/295547 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4877 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14295547 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/295547
Integrated circuits with hall effect sensors and methods for producing such integrated circuits Jun 3, 2014 Issued
Array ( [id] => 11770596 [patent_doc_number] => 09379297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'LED light source package' [patent_app_type] => utility [patent_app_number] => 14/296188 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296188
LED light source package Jun 3, 2014 Issued
Array ( [id] => 10042127 [patent_doc_number] => 09082841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-14 [patent_title] => 'Semiconductor device having metal layer over drift region' [patent_app_type] => utility [patent_app_number] => 14/296268 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296268
Semiconductor device having metal layer over drift region Jun 3, 2014 Issued
Array ( [id] => 10472430 [patent_doc_number] => 20150357446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/295377 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14295377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/295377
Bipolar transistor structure and a method of manufacturing a bipolar transistor structure Jun 3, 2014 Issued
Array ( [id] => 10472325 [patent_doc_number] => 20150357341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'MULTI-LAYER MEMORY ARRAY AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/296173 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296173
Multi-layer memory array and manufacturing method of the same Jun 3, 2014 Issued
Array ( [id] => 10472422 [patent_doc_number] => 20150357439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS' [patent_app_type] => utility [patent_app_number] => 14/295618 [patent_app_country] => US [patent_app_date] => 2014-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2194 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14295618 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/295618
Method for making semiconductor device with isolation pillars between adjacent semiconductor fins Jun 3, 2014 Issued
Array ( [id] => 10463834 [patent_doc_number] => 20150348849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'TRANSISTOR WITH EMBEDDED STRESS-INDUCING LAYERS' [patent_app_type] => utility [patent_app_number] => 14/294467 [patent_app_country] => US [patent_app_date] => 2014-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14294467 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/294467
Transistor with embedded stress-inducing layers Jun 2, 2014 Issued
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