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Thien Dang Nguyen

Examiner (ID: 2181, Phone: (571)272-9189 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2111, 2117
Total Applications
814
Issued Applications
675
Pending Applications
59
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20043227 [patent_doc_number] => 20250181449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => Tracking Circuitry with Source Identification for Uncorrectable Memory Errors [patent_app_type] => utility [patent_app_number] => 19/045110 [patent_app_country] => US [patent_app_date] => 2025-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19045110 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/045110
Tracking Circuitry with Source Identification for Uncorrectable Memory Errors Feb 3, 2025 Pending
Array ( [id] => 20036068 [patent_doc_number] => 20250174290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR DEVICE PERFORMING DATA READ OPERATION AND CONTROLLER CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 19/038044 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038044 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/038044
SEMICONDUCTOR DEVICE PERFORMING DATA READ OPERATION AND CONTROLLER CONTROLLING THE SAME Jan 26, 2025 Pending
Array ( [id] => 20029589 [patent_doc_number] => 20250167811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SYSTEMS FOR ERROR REDUCTION OF ENCODED DATA USING NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 19/028790 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19028790 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/028790
SYSTEMS FOR ERROR REDUCTION OF ENCODED DATA USING NEURAL NETWORKS Jan 16, 2025 Pending
Array ( [id] => 20020517 [patent_doc_number] => 20250158739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS [patent_app_type] => utility [patent_app_number] => 19/026299 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19026299 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/026299
SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS Jan 15, 2025 Pending
Array ( [id] => 20738379 [patent_doc_number] => 20260147681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => METHOD OF GENERATING TEST SEQUENCE OF ECU AND TEST SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 19/016161 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19016161 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/016161
METHOD OF GENERATING TEST SEQUENCE OF ECU AND TEST SYSTEM THEREOF Jan 9, 2025 Pending
Array ( [id] => 19992667 [patent_doc_number] => 20250130889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ERROR CORRECTION CODING DEVICE AND ERROR CORRECTION CODING METHOD [patent_app_type] => utility [patent_app_number] => 19/000063 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000063 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/000063
ERROR CORRECTION CODING DEVICE AND ERROR CORRECTION CODING METHOD Dec 22, 2024 Pending
Array ( [id] => 20011981 [patent_doc_number] => 20250150203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => METHODS AND SYSTEMS FOR DATA TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/985491 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18985491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/985491
METHODS AND SYSTEMS FOR DATA TRANSMISSION Dec 17, 2024 Pending
Array ( [id] => 20064285 [patent_doc_number] => 20250202507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => PROCESSING SYSTEM AND METHOD USING A TWEAKABLE CODE-BASED MASKING [patent_app_type] => utility [patent_app_number] => 18/977174 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977174
PROCESSING SYSTEM AND METHOD USING A TWEAKABLE CODE-BASED MASKING Dec 10, 2024 Pending
Array ( [id] => 20027624 [patent_doc_number] => 20250165846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => IMPROVED ERROR DETECTION MECHANISM FOR QUANTUM BITS [patent_app_type] => utility [patent_app_number] => 18/974857 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974857
IMPROVED ERROR DETECTION MECHANISM FOR QUANTUM BITS Dec 9, 2024 Pending
Array ( [id] => 19848934 [patent_doc_number] => 20250094285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PROGRAMMABLE IO MODULE [patent_app_type] => utility [patent_app_number] => 18/972707 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18972707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/972707
PROGRAMMABLE IO MODULE Dec 5, 2024 Pending
Array ( [id] => 20249824 [patent_doc_number] => 20250298693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => ERROR CORRECTION CODE CIRCUIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/970334 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970334 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970334
ERROR CORRECTION CODE CIRCUIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION FOR MEMORY DEVICE Dec 4, 2024 Pending
Array ( [id] => 20060844 [patent_doc_number] => 20250199066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => TEST IMPLEMENTATION [patent_app_type] => utility [patent_app_number] => 18/967975 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967975
TEST IMPLEMENTATION Dec 3, 2024 Pending
Array ( [id] => 20751929 [patent_doc_number] => 20260154157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => LOW COMPLEXITY BIT-ERROR-RATE ESTIMATION FOR ENCODED FOGGY-FINE PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/968099 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968099
Low complexity bit-error-rate estimation for encoded foggy-fine programming Dec 3, 2024 Issued
Array ( [id] => 20921890 [patent_doc_number] => 12716945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Secure scan testing of integrated circuits [patent_app_type] => utility [patent_app_number] => 18/959204 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959204 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/959204
SECURE SCAN TESTING OF INTEGRATED CIRCUITS Nov 24, 2024 Pending
Array ( [id] => 20740160 [patent_doc_number] => 20260149469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => DECODING SCHEMES FOR UNEQUAL MESSAGE PROTECTION USING NESTED SUBCODES IN REED-MULLER CODES [patent_app_type] => utility [patent_app_number] => 18/957538 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/957538
DECODING SCHEMES FOR UNEQUAL MESSAGE PROTECTION USING NESTED SUBCODES IN REED-MULLER CODES Nov 21, 2024 Pending
Array ( [id] => 20018048 [patent_doc_number] => 20250156270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MONITORING FEC INFORMATION IN MULTI-CHIP ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/948254 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948254
MONITORING FEC INFORMATION IN MULTI-CHIP ENVIRONMENT Nov 13, 2024 Pending
Array ( [id] => 19804999 [patent_doc_number] => 20250070924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => METHODS, SYSTEMS AND APPARATUS FOR SCHEDULING OF HYBRID AUTOMATIC REPEAT REQUEST (HARQ) FEEDBACK [patent_app_type] => utility [patent_app_number] => 18/943077 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943077
METHODS, SYSTEMS AND APPARATUS FOR SCHEDULING OF HYBRID AUTOMATIC REPEAT REQUEST (HARQ) FEEDBACK Nov 10, 2024 Pending
Array ( [id] => 20827522 [patent_doc_number] => 12681082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 18/939967 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939967
Electronic device Nov 6, 2024 Issued
Array ( [id] => 20487447 [patent_doc_number] => 20260023646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => PHYSICAL MEMORY BLOCK HEALTH BASED VIRTUAL BLOCK [patent_app_type] => utility [patent_app_number] => 18/940056 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940056
PHYSICAL MEMORY BLOCK HEALTH BASED VIRTUAL BLOCK Nov 6, 2024 Pending
Array ( [id] => 20696699 [patent_doc_number] => 20260128112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => MEMORY MIRROR SEQUENCING FOR REDUCED LATENCY IN MEMORY PATCHING [patent_app_type] => utility [patent_app_number] => 18/940473 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940473
MEMORY MIRROR SEQUENCING FOR REDUCED LATENCY IN MEMORY PATCHING Nov 6, 2024 Pending
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